參數(shù)資料
型號(hào)： SAA5288PS
廠商： NXP Semiconductors N.V.
英文描述： TV microcontroller with full screen On Screen Display OSD
中文描述： 微控制器與電視屏幕顯示OSD全屏
文件頁(yè)數(shù)： 8/48頁(yè)
文件大小： 508K
代理商： SAA5288PS
1997 Jun 24
8
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen
On Screen Display (OSD)
SAA5288
7
FUNCTIONAL DESCRIPTION
7.1
Microcontroller
The functionality of the microcontroller used with this
family is described with reference to the industry-standard
80C51 microcontroller. A full description of its functionality
can be found in “80C51-Based; 8-bit Microcontrollers,
Data Handbook IC20” Using the 80C51 as a reference,
the changes made to this family fall into two categories:
Features not supported by the SAA5288
Features found on the SAA5288 but not supported by
the 80C51.
7.2
80C51 features not supported
7.2.1
I
NTERRUPT PRIORITY
The IP SFR is not implemented and all interrupts are
treated with the same priority level. The normal priority of
interrupts is maintained within the level.
Table 2
Interrupts and vector address
7.2.2
O
FF
-
CHIP MEMORY
The SAA5288 does not support the use of off-chip
program memory or off-chip data memory.
7.2.3
I
DLE AND
P
OWER
-
DOWN MODES
Idle and Power-down modes are not supported.
Consequently, the respective bits in PCON are not
available.
7.2.4
UART
FUNCTION
The 80C51 UART is not available. As a consequence the
SCON and SBUF SFRs are removed and the ES bit in the
IE SFR is unavailable.
INTERRUPT SOURCE
VECTOR ADDRESS
(HEX)
Reset
External INT0
Timer 0
External INT1
Timer 1
Byte I
2
C-bus
Bit I
2
C-bus
000
003
00B
013
01B
02B
053
7.3
Additional features
The following features are provided in addition to the
standard 80C51 features.
7.3.1
I
NTERRUPTS
The external INT1 interrupt is modified to generate an
interrupt on both the rising and falling edges of the INT1
pin, when EX1 bit is set. This facility allows for software
pulse-width measurement for handling of a remote control.
7.3.2
B
IT
L
EVEL
I
2
C-
BUS
I
NTERFACE
For reasons of compatibility with the SAA5290, SAA5291,
SAA5291A and SAA5491 all contain a bit level serial I/O
which supports the I
2
C-bus. P1.6/SCL and P1.7/SDA are
the serial I/O pins. These two pins meet the I
2
C-bus
specification concerning the input levels and output drive
capability see “The I
2
C-bus and how to use it (including
specifications)” Consequently, these two pins have an
open-drain output configuration. All the four following
modes of the I
2
C-bus are supported.
Master transmitter
Master receiver
Slave transmitter
Slave receiver.
Three SFRs support the function of the bit-level I
2
C-bus
hardware: S1INT, S1BIT and S1SCS and are enabled by
setting register bit TXT8.I
2
C SELECT to logic 0.
7.3.3
B
YTE
L
EVEL
I
2
C-
BUS
I
NTERFACE
The byte level serial I/O supports the I
2
C-bus protocol.
P1.6/SCL and P1.7/SDA are the serial I/O pins. These two
pins meet the I
2
C-bus specification concerning the input
levels and output drive capability. Consequently, these two
pins have an open-drain output configuration.
The byte level I
2
C-bus serial port is identical to the I
2
C-bus
serial port on the 8xC552. The operation of the subsystem
is described in detail in the 8xC552 data sheet described
in “80C51-Based; 8-bit Microcontrollers Data Handbook
IC20”
Four SFRs support the byte level I
2
C-bus hardware:
S1CON, S1STA, S1DAT and S1ADR. They are enabled
by setting register bit TXT8. I
2
C SELECT to logic 1.
7.3.4
LED
SUPPORT
Port pins P0.5 and P0.6 have a 10 mA current sinking
capability to enable LEDs to be driven directly.
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