參數(shù)資料
型號(hào): SAA5284GP
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: Multimedia video data acquisition circuit
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝: 14 X 14 X 2.20 MM, PLASTIC, QFP-44
文件頁數(shù): 8/24頁
文件大?。?/td> 159K
代理商: SAA5284GP
1998 Feb 05
8
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
8.9
Host interface
The SAA5284 has a multi-standard 8-bit I/O interface.
To reduce the amount of host I/O space used, the parallel
interface has only 3 address inputs (A0, A1 and A2).
An extended addressing (pointer) scheme and the data
FIFO are used to allow access to the full set of SAA5284
registers and the full span of the packet buffer.
As well as the 8 data I/O lines and 3 address lines, there
are the following control signals: RD (read LOW), WR
(write LOW), CS0 (chip select LOW), CS1(second chip
select LOW), INT (interrupt request), DMARQ (DMA
request), DMACK (DMA acknowledge) and RDY (ready).
In order to maintain compatibility with Motorola and Intel
type buses, two control signals SEL0 and SEL1 are
provided to configure the host interface. These signals
allow configuration of the host interface to work with the
Motorola or Intel style interfaces.
The host interface has a digital video mode. Digital video
mode may be used to allow the SAA5284 to pass decoded
VBI data into a system using the digital video bus.
8.10
Interrupt support
The host interface provides comprehensive support for
interrupt generation. The interrupt may be programmed to
occur when a particular number of packets of VBI data are
available in the cache RAM. The interrupts can be further
controlled to occur on a specific line in the TV frame.
The interrupts can also be self masking if required.
8.11
DMA support
Burst and demand mode DMA are supported. In burst
mode, the number of packets to transfer can be defined.
An interrupt can be generated when DMA is finished. This
can be self masking.
8.12
I
2
C-bus interface
The I
2
C-bus interface functions as a slave receiver or
transmitter at up to 400 kHz. The I
2
C-bus address is
selectable as 20H or 22H. All functionality is available
using the I
2
C-bus although with a slower data transfer
speed. It is possible to use the I
2
C-bus in all modes.
9
In accordance with the Absolute Maximum Rating System (IEC 134).
LIMITING VALUES
10 QUALITY & RELIABILITY
In accordance with “SNW-FQ-611-E”
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
V
DD
V
I(max)
V
O(max)
V
DDD
DDA
DDX
supply voltage difference between V
DDD
, V
DDA
and V
DDX
I
IOK
DC input or output diode current
I
O(max)
output current (any output)
T
stg
storage temperature
T
amb
operating ambient temperature
supply voltage (all supplies)
input voltage (any input)
output voltage (any output)
0.3
0.3
0.3
55
20
+6.5
V
DD
+ 0.5
V
DD
+ 0.5
0.25
20
10
+125
+70
V
V
V
V
mA
mA
°
C
°
C
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