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參數(shù)資料
| 型號： | SAA2510 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Video CD VCD decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 20 X 2.70 MM, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 126K |
| 代理商： | SAA2510 |
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1996 May 21
9
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
FUNCTIONAL DESCRIPTION
Block decoder
The VCD chip receives MPEG A/V or CD digital audio data
from a CD decoder chipset using any one of four common
interface formats (Philips I
2
S, EIAJ, MEC or IEC 958). The
Philips I
2
S, EIAJ and Matsushita input modes use the bit
clock (CLIN), word select (WSIN), data (DAIN) and error
flag (EFIN) inputs. If IEC 958 (EBU) input mode is
selected, only the EBUIN pin needs to be connected. The
chip also requires a 16.9 MHz clock input (CLIN) which is
synchronous with the data input from the CD decoder
providing the serial data input.
The VCD chip contains a block decoder and descrambler
which performs error correction on the Video CD data track
(form 1) sectors and error detection on real-time audio and
video tracks where an error correction code is present.
In most events, audio output can be in any of the three
(I
2
S, EIAJ or MEC) formats, independent of input type.
When playing CD digital audio discs, the input is copied to
the outputs.
The block decoder supports some special functions which
enable recovery of play control lists. The desired sectors
can be acquired by programming a sector address via the
I
2
C-bus microcontroller interface. The microcontroller then
instructs the CD servo/decoder subsystem to execute a
servo jump to the required disc location and then waits for
an interrupt indicating that the desired sector information
has been received and error-corrected.
System controller
Overall control of the chip and a number of its less
time-critical functions is carried out by a dedicated
RISC processor. The microcode for this processor is
executed from an on-chip RAM. This microcode must be
loaded into RAM after power-up by the host
microcontroller, using the I
2
C-bus interface. This enables
the functionality of the chip to be customized for specific
applications.
On-screen display
The VCD chip provides a bit-mapped On-Screen-Display
(OSD), containing 32 display lines of 352 pixels per line.
There is a double-height mode which repeats OSD lines so
that the maximum height of OSD objects becomes
64 lines. This character-set-independent OSD permits
display of ideographic characters and simple graphic
displays anywhere on the screen.
The OSD is implemented as 48 vertical ‘slices’ of 8 pixels
(horizontally) and 32 (vertically). Each pixel is stored as
2 bits. This gives three programmable logical colours, plus
a transparent option. Each slice is identified by a slice code
(slice number).
The horizontal position of a slice is defined by its position
in a slice code sequence written to the VCD chip. This
arrangement reduces the need to completely update the
OSD bit map in many situations. It may be possible to
simply reorder the slices, e.g. if a track time display is
being updated and slices are prepared to represent digits.
At any time, up to 44 of the 48 slices can be displayed.
Video decoder
Video output data can be presented in one of two modes:
1.
16-bit wide data is output in YUV 4 : 2 : 2 format as
8 bits of luminance and 8 bits of alternating U and
V chrominance. The video output data rate in this
mode is 13.5 Mwords/s.
2.
8-bit wide, CCIR656-like, data is output providing
4 : 2 : 2 format video as an 8-bit UYVY multiplex at
27 Mbytes/s.
In either case, the VCD chip can be programmed to output
525 line or 625 line format timing to match the type of
display (TV) connected to its output. Additional
programmability is provided to cope with the Video CD disc
source picture coding type (525/625 lines).
The VCD chip performs vertical and horizontal
interpolation to convert the MPEG SIF (352 pixels per line)
normal resolution pictures to CCIR601 resolution.
Vertically interpolated pixels are output on the odd fields
during display of normal resolution pictures.
The Video CD disc being played may have been coded
with 525 lines/60 Hz or 625 lines/50 Hz pictures. When the
Video CD player is connected to a display with a different
timebase to the coded disc material, some adjustments
must be made to allow for the different number of lines on
the display and the reconstructed picture. Two examples
are shown in Figs. 3 and 4.
The VCD chip can be programmed to position the
reconstructed picture with respect to horizontal and
vertical syncs anywhere on the display screen with a
programmable ‘viewport’ position. Figure 3 shows an
MPEG SIF resolution picture (352 pixels by 288 lines)
being displayed on an NTSC display having only
240 active display lines per field. In this event, the top and
bottom 24 lines are not displayed.
相關PDF資料 |
PDF描述 |
|---|---|
| SAA2520GP | Stereo filter and codec for MPEG layer 1 audio applications |
| SAA2520 | Stereo filter and codec for MPEG layer 1 audio applications |
| SAA3004 | Remote control transmitter |
| SAA3004P | Remote control transmitter |
| SAA3004T | Remote control transmitter |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA2511DEB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic |
| SAA2520 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Stereo filter and codec for MPEG layer 1 audio applications |
| SAA2520GP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Stereo filter and codec for MPEG layer 1 audio applications |
| SAA2521 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Masking threshold processor for MPEG layer 1 audio compression applications |
| SAA2521GP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Masking threshold processor for MPEG layer 1 audio compression applications |
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