參數(shù)資料
型號: SAA2510
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: Video CD VCD decoder
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: 14 X 20 X 2.70 MM, PLASTIC, QFP-100
文件頁數(shù): 11/28頁
文件大小: 126K
代理商: SAA2510
1996 May 21
11
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
‘Trickmode’ implementation
Compared with CD digital audio players, it is likely that
Video CD players will need to offer additional functionality
similar to VCRs. These features are commonly called
‘trickmodes’. Typically, the player will offer features such
as still picture (freeze frame), scan forwards and
backwards as well as slow motion replay.
These features require a combination of CD servo control
and Video CD decoder functions for effective
implementation. The VCD chip provides high level
command features to support these modes in order to
minimize microcontroller time-critical software.
S
TILL PICTURE DISPLAY
This is implemented directly using a Pause command,
causing the VCD chip to hold the displayed picture at the
next frame update.
S
CAN FORWARD AND SCAN BACKWARDS
There is no difference as far as the VCD chip is concerned.
The controlling microcomputer must command the CD
servo to execute a servo jump and re-synchronize. The
VCD chip is then commanded to display the next I
(Intra-coded) picture following re-acquisition of sector
sync.
S
LOW
-
MOTION REPLAY
A command is provided by the VCD chip, allowing a
slow-motion ‘factor’ in the range 2 to 8 to be selected. This
is the factor by which replay will be slowed down. Because
the rate of decoding of video sectors has been reduced,
the video FIFO fills up. The block decoder is designed to
automatically disable acquisition when the video FIFO fills
in this way and an interrupt is generated. At this point, the
next wanted sector (address) has been loaded into a
register in the VCD chip. The controlling microcomputer
then commands a CD servo jump to position on the disc
just before the next desired sector, making allowance for
re-synchronization by the servo and VCD chip.
I
2
C-bus interface
The VCD chip is programmed via the I
2
C-bus interface.
The chip is a slave transceiver capable of operating at the
maximum specified bus clock frequency of 400 kHz. It
does not support the general call feature. One of two slave
addresses can be used. The address is selected by the
ASEL input pin.
This bus provides access to the internal registers of the
device. The bus is also used to write OSD slice data and
to read data stored in three play-control sector buffers,
which normally will be used to store Video CD data track
information. This interface features a two or three byte
sub-addressing scheme allowing access to any DRAM
location. However, in normal use, only two byte
sub-addressing is needed.
An interrupt pin is available to signal a number of events
so that the controlling processor does not need to poll VCD
status registers.
Input pin NDAV is used to signal that data on the block
decoder input is not valid, e.g. during CD servo jumps.
A complete memory map and list of registers will be
included in a later version of this data sheet.
I
2
C-bus slave address selection
Note
1.
ASEL.
The data transfer protocol is as follows:
Two and three byte sub-addressing: first the device
sub-address is transmitted, preceded by a START
condition and the slave address:
Two and three byte sub-addressing
The sub-address can be either 2 or 3 bytes. The 3-byte
sub-address is used for DRAM random access. This is not
used for normal operation. It exists only as a test mode.
Since the Video CD IC is internally fully word (16 bits)
oriented, the sub-address must always be an even
address. If an odd-numbered address is given, the Video
CD IC will not acknowledge this byte. For the sub-address,
the least significant byte is sent first. The second
sub-address byte contains 2 control bits.
A6
0
A5
0
A4
1
A3
1
A2
0
A1
1
A0
A0
(1)
R/W
S
SLA
W
SUB_A
S = START
SLA = Slave address
W = Write
SUB_A = Sub-address
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