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參數(shù)資料
| 型號： | SA7026DH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | 1.3GHz low voltage fractional-N dual frequency synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO20 |
| 封裝： | 4.40 MM, PLASTIC, SOT-360-1, TSSOP-20 |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 299K |
| 代理商： | SA7026DH |
Philips Semiconductors
Product specification
SA7026
1.3GHz low voltage fractional-N dual synthesizer
1999 Nov 04
5
CHARACTERISTICS
V
DDCP
= V
DD
= +3.0V,
T
amb
= +25
°
C;
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply; pins 3, 13
V
DD
Digital supply voltage
2.7
–
5.5
V
V
DDCP
Analog supply voltage
V
DDCP
V
DD
2.7
–
5.5
V
I
DDTotal
Synthesizer operational total supply current
V
= +3.0V
(with main and aux on)
–
7.5
8.8
mA
I
Standby
Total supply current in power-down mode
logic levels 0 or V
DD
–
1
–
μΑ
RFin main divider input; pins 5, 6
f
VCO
VCO input frequency
350
–
1300
MHz
V
RFin(rms)
AC-coupled input signal level
R
(external) = R
= 50
;
single-ended drive;
max. limit is indicative
@ 500 to 1300 MHz
–18
–
0
dBm
Z
IRFin
Input impedance (real part)
f
VCO
= 1.2 GHz
–
300
–
C
IRFin
Typical pin input capacitance
f
VCO
= 1.2 GHz
–
1
–
pF
N
main
Main divider ratio
512
–
65535
f
PCmax
Maximum loop comparison frequency
indicative, not tested
–
–
4
MHz
AUX reference divider input; pin 12
f
AUXin
Input frequency range
20
–
550
MHz
V
AUXin
AC coupled input signal level
AC-coupled input signal level
R
(
= 50
;
max. limit is indicative
–18
–
0
dBm
80
–
632
mV
PP
Z
AUXin
Input impedance (real part)
f
VCO
= 500 MHz
–
3.9
–
k
C
AUXin
Typical pin input capacitance
f
VCO
= 500 MHz
–
1
–
pF
N
AUX
Auxiliary division ratio
128
–
16383
Reference divider input; pins 15, 16
f
REFin
Input frequency range from TCXO
5
–
40
MHz
V
RFin
AC-coupled input signal level
single-ended drive;
max. limit is indicative
360
–
1300
mV
PP
Z
REFin
Input impedance (real part)
f
REF
= 20 MHz
–
10
–
k
C
REFin
Typical pin input capacitance
f
REF
= 20 MHz
–
1
–
pF
R
REF
Reference division ratio
SA = SM = ”000”
4
–
1023
Charge pump current setting resistor input; pin 14
R
SET
External resistor from pin to ground
6
7.5
15
k
V
SET
Regulated voltage at pin
R
SET
= 7.5 k
–
1.25
–
V
Charge pump outputs (including fractional compensation pump); pins 8, 9, 11; R
SET
= 7.5 k
, FC = 80
Charge pump current ratio to I
SET1
I
CP
Current gain = I
PH
/I
SET
–15
+15
%
I
MATCH
Sink-to-source current matching
V
PH
= 1/2 V
DDCP
–10
+10
%
I
ZOUT
Output current variation versus V
PH2
V
PH
in compliance range
–10
+10
%
I
LPH
Charge pump off leakage current
V
PH
= 1/2 V
DDCP
–10
+10
nA
V
PH
Charge pump voltage compliance
0.7
–
V
DDCP
–0.8
V
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