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參數(shù)資料
| 型號(hào)： | SA7016DH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | 1.3GHz low voltage fractional-N synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16 |
| 封裝： | PLASTIC, TSSOP-16 |
| 文件頁(yè)數(shù)： | 10/18頁(yè) |
| 文件大?。?/td> | 232K |
| 代理商： | SA7016DH |
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Philips Semiconductors
Product specification
SA7016
1.3GHz low voltage fractional-N synthesizer
1999 Nov 04
10
Charge pump currents
CP0
I
PHP
I
PHP–SU
0
3xI
SET
15xl
SET
1
1xl
SET
5xl
SET
NOTES:
1. I
SET
=V
SET
/R
SET
: bias current for charge pumps.
2. I
PHP–SU
is the total current at pin PHP during speed up condition.
Lock Detect
The output LOCK maintains a logic ‘1’ when the auxiliary phase
detector ANDed with the main phase detector indicates a lock
condition. The lock condition for the main and auxiliary synthesizers
is defined as a phase difference of less than
frequency at the input REFin+, –. One counter can fulfill the lock
condition when the other counter is powered down. Out of lock (logic
‘0’) is indicated when both counters are powered down.
1 period of the
Power-down mode
The power-down signal can be either hardware (PON) or software
(PD). The PON signal is exclusively ORed with the PD bits in
B-word. If PON = 0, then the part is powered up when PD = 1. PON
can be used to invert the polarity of the software bit PD. When the
synthesizer is reactivated after power-down, the main and reference
dividers are synchronized to avoid possibility of random phase
errors on power-up.
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| SA701D | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Divide by: 128/129-64/65 dual modulus low power ECL prescaler |
| SA701N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Divide by: 128/129-64/65 dual modulus low power ECL prescaler |
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| SA702/DF9M(62) | 制造商:Hirose 功能描述:903-4508-0-62 EACH 制造商:Hirose 功能描述:SA702/DF9M(62) |
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