參數(shù)資料
型號: SA58643
廠商: NXP Semiconductors N.V.
英文描述: Single-Pole Double-Throw (SPDT) switch
中文描述: 單刀雙擲(SPDT)開關(guān)
文件頁數(shù): 8/16頁
文件大?。?/td> 153K
代理商: SA58643
SA58643_1
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 20 November 2006
8 of 16
NXP Semiconductors
SA58643
Single-Pole Double-Throw (SPDT) switch
13. Application information
13.1 Evaluation demo board
The typical applications schematic and printed-circuit board layout of the SA58643
evaluation board is shown in
Figure 19
. The layout of the board is simple, but a few
cautions need to be observed. The input and output traces should be 50
. The
placement of the AC bypass capacitor is extremely critical if a symmetric isolation
between the two channels is desired. The trace from pin 7 (AC_GND) should be drawn
back towards the package and then be routed downwards. The capacitor should be
placed straight down as close to the device as practical. For better isolation between the
two channels at higher frequencies, it is also advisable to run the two output/input traces
at an angle. This also minimizes any inductive coupling between the two traces. The
power supply bypass capacitor should be placed close to the device.
Figure 5
shows the
frequency response of the SA58643. The loss matching between the two channels is
excellent to 1.2 GHz as shown in
Figure 7
.
a. Evaluation board schematic
b. SA58643 board layout
Fig 19. Evaluation board and layout
002aab691
V
DD
+5 V
0.1
μ
F
0.01
μ
F
INPUT
SA58643
OUT1
ENCH1
AC_GND
GND
GND
OUT2
1
2
3
4
6
5
8
7
DP package
0.01
μ
F
0.01
μ
F
0.01
μ
F
ENCH1
C2
U1
C6
A
B
Test Line
SA58643 TSSOP8
#30007-A50
C3
C5
C4
OUT1
OUT2
Analog GND
G
V
ENCH1
C2
U1
C6
A
B
Test Line
SA58643 TSSOP8
#30007-A50
C3
C5
C4
OUT1
OUT2
Analog GND
G
V
C1
C1
top view
bottom view
002aab692
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