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參數資料
| 型號： | SA1620 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low voltage GSM front-end transceiver(低壓GSM前端收發(fā)器) |
| 中文描述： | 低電壓的GSM前端收發(fā)器（低壓手機前端收發(fā)器） |
| 文件頁數： | 5/26頁 |
| 文件大?。?/td> | 203K |
| 代理商： | SA1620 |
Philips Semiconductors
Product specification
SA1620
Low voltage GSM front-end transceiver
1997 May 22
5
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNITS
V
CCXX
V
BATT
V
IN
V
VG
Supply voltages
-0.3 to +6.0
V
Battery voltage
-0.3 to +8.0
V
Voltage applied to any other pin
-0.3 to (V
CCXX
+0.3)
-0.3 to +1
V
V
CC
Tx1,2 pins to V
CC
BM
Any GND pin to any other GND pin
V
0
V
P
D
Power dissipation, T
A
= 25
°
C (still air)
Maximum operating junction temperature
800
mW
T
JMAX
P
MAX
T
STG
150
°
C
Maximum power input/output
+20
dBm
Storage temperature range
–65 to +150
°
C
V
TXO
, V
TXOX
V
RXIF
, V
RXIFX
NOTE:
1. Maximum junction temperature is determined by the power dissipation is determined by the operating ambient temperature and the thermal
resistance,
θ
JA
. 48-pin TQFP:
θ
JA
= 67
°
C/W.
Positive RF peak voltage at Tx outputs
6
V
Positive IF peak voltage at Rx mixer outputs
6
V
DC REGULATORS
Two low drop regulators (REG1 and REG2) are included on the chip
and may be used to deliver the supply voltage of the main circuitry
(e.g., 3V) out of the battery (at V
BATT
= 3.3 to 7.5V) as shown in
Figure 4 and in Table 1.
REG1 is intended to supply, at least, the internal functions of the
SA1620. Both regulators may also be used for external circuitry.
For this application, different voltages may be programmed as
shown in Table 1.
The transmitter supply pins (V
CC
Tx1,2) also operate as a sensor
connection in the feedback loop of REG1 and must be externally
connected to pin VREG1. For REG2, the sensor pin VREGF2 must
be connected to VREG2.
All ground pins are internally bonded to the header except for pins
GNDL1, GNDREG1 and GNDREG2.
When both regulators are not used, connect pins V
BATT
, PON,
CON1, CON2, VREG1, VREG2 and VREG2F2 to ground.
Table 1.
DC Reg Output Voltage Control Pins
CON1
CON2
VREG1
VREG2
UNITS
L
L
3
±
5%
3.4
±
5%
3.7
±
5%
5.1
±
5%
3
±
5%
3.4
±
5%
3.7
±
5%
5.1
±
10%
V
L
H
V
H
L
V
H
H
V
NOTES:
1. Logic levels at CON1 and CON2:
H – Open circuit. Pin must not be connected externally.
Logic high level supplied on chip.
L – Connected to ground.
2. Currents at CON1 and CON2:
H – 0
μ
A
L (PON = H) – 50
μ
A
L (PON = L) – <1
μ
A
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