163
32072H–AVR32–10/2012
AT32UC3A3
14. External Bus Interface (EBI)
Rev.: 1.7.0.1
14.1
Features
Optimized for application memory space support
Integrates three external memory controllers:
– Static Memory Controller (SMC)
– SDRAM Controller (SDRAMC)
– Error Corrected Code (ECCHRS) controller
Additional logic for NAND Flash/SmartMediaTM and CompactFlashTM support
– NAND Flash support: 8-bit as well as 16-bit devices are supported
– CompactFlash support: Attribute Memory, Common Memory, I/O modes are supported but
the signal _IOIS16 (I/O mode) is not handled.
Optimized external bus:16-bit data bus
– Up to 24-bit Address Bus, Up to 8-Mbytes Addressable
– Optimized pin multiplexing to reduce latencies on external memories
Up to 6 Chip Selects, Configurable Assignment:
– Static Memory Controller on Chip Select 0
– SDRAM Controller or Static Memory Controller on Chip Select 1
– Static Memory Controller on Chip Select 2, Optional NAND Flash support
– Static Memory Controller on Chip Select 3, Optional NAND Flash support
– Static Memory Controller on Chip Select 4, Optional CompactFlashTM support
– Static Memory Controller on Chip Select 5, Optional CompactFlashTM support
14.2
Overview
The External Bus Interface (EBI) is designed to ensure the successful data transfer between
several external devices and the embedded memory controller of an 32-bit AVR device. The
Static Memory, SDRAM and ECCHRS Controllers are all featured external memory controllers
on the EBI. These external memory controllers are capable of handling several types of external
memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, and
SDRAM.
The EBI also supports the CompactFlash and the NAND Flash/SmartMedia protocols via inte-
grated circuitry that greatly reduces the requirements for external components. Furthermore, the
EBI handles data transfers with up to six external devices, each assigned to six address spaces
defined by the embedded memory controller. Data transfers are performed through a 16-bit, an
address bus of up to 23 bits, up to six chip select lines (NCS[5:0]), and several control pins that
are generally multiplexed between the different external memory controllers.