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型號(hào)：	S80C52XXX-12SHXXX:R
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁(yè)數(shù)：	292/1021頁(yè)
文件大?。?/td>	15196K

32072H–AVR32–10/2012

AT32UC3A3

Multi-block Transfer with Source Address Auto-reloaded and Contiguous Destination Address (Row 3)

Read the Channel Enable register to choose a free (disabled) channel.

Clear any pending interrupts on the channel from the previous DMA transfer by writing

a ‘1’ to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran,

ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that

all interrupts have been cleared.

Program the following channel registers:

Write the starting source address in the SARx register for channel x.

Write the starting destination address in the DARx register for channel x.

Program CTLx and CFGx according to Row 3 as shown in Table 19-1 on page 327.

Program the LLPx register with ‘0’.

Write the control information for the DMA transfer in the CTLx register for channel

x. For example, in this register, you can program the following:

– i. Set up the transfer type (memory or non-memory peripheral for source and

destination) and flow control device by programming the TT_FC of the CTLx register.

– ii. Set up the transfer characteristics, such as:

– Transfer width for the source in the SRC_TR_WIDTH field.

– Transfer width for the destination in the DST_TR_WIDTH field.

– Source master layer in the SMS field where source resides.

– Destination master layer in the DMS field where destination resides.

– Incrementing/decrementing or fixed address for source in SINC field.

– Incrementing/decrementing or fixed address for destination in DINC field.

Write the channel configuration information into the CFGx register for channel x.

– i. Designate the handshaking interface type (hardware or software) for the source

and destination peripherals. This is not required for memory. This step requires

programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’

activates the hardware handshaking interface to handle source/destination requests

for the specific channel. Writing a ‘1’ activates the software handshaking interface to

handle source/destination requests.

– ii. If the hardware handshaking interface is activated for the source or destination

peripheral, assign handshaking interface to the source and destination peripheral.

This requires programming the SRC_PER and DEST_PER bits, respectively.

After the DMACA channel has been programmed, enable the channel by writing a ‘1’ to

the ChEnReg.CH_EN bit. Make sure that bit 0 of the DmaCfgReg register is enabled.

Source and destination request single and burst DMACA transactions to transfer the

block of data (assuming non-memory peripherals). The DMACA acknowledges at the

completion of every transaction (burst and single) in the block and carries out the block

When the block transfer has completed, the DMACA reloads the SARx register. The

DARx register remains unchanged. Hardware sets the block complete interrupt. The

DMACA then samples the row number as shown in Table 19-1 on page 327. If the

DMACA is in Row 1, then the DMA transfer has completed. Hardware sets the transfer

complete interrupt and disables the channel. So you can either respond to the Block

Complete or Transfer Complete interrupts, or poll for the Channel Enable (ChEn-

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C54	制造商:INTEL 制造商全稱:Intel Corporation 功能描述:CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
S80C54-1	制造商:INTEL 制造商全稱:Intel Corporation 功能描述:CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
S80C54-2	制造商:INTEL 制造商全稱:Intel Corporation 功能描述:CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
S80C54-20	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C54-24	制造商:INTEL 制造商全稱:Intel Corporation 功能描述:CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

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