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型號：	S80C52XXX-12SHXXX:R
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁數(shù)：	7/1021頁
文件大小：	15196K

32072H–AVR32–10/2012

AT32UC3A3

Clearing the NAK bit before the BTF bit is set locks up the TWI bus

When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg-

ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to

attempt to continue transmitting data, thus locking up the bus.

Fix/Workaround

Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been

TWIS stretch on Address match error

When the TWIS stretches TWCK due to a slave address match, it also holds TWD low for

the same duration if it is to be receiving data. When TWIS releases TWCK, it releases TWD

at the same time. This can cause a TWI timing violation.

Fix/Workaround

MCI_CLK features is not available on PX12, PX13 and PX40

Fix/Workaround

MCI_CLK feature is available on PA27 only.

The busy signal of the responses R1b is not taken in account for CMD12

STOP_TRANSFER

It is not possible to know the busy status of the card during the response (R1b) for the com-

mands CMD12.

Fix/Workaround

The card busy line should be polled through the GPIO Input Value register (IVR) for com-

mands CMD12.

Frame Synchro and Frame Synchro Data are delayed by one clock cycle

The frame synchro and the frame synchro data are delayed from 1 SSC_CLOCK when:

- Clock is CKDIV

- The START is selected on either a frame synchro edge or a level

- Frame synchro data is enabled

- Transmit clock is gated on output (through CKO field)

Fix/Workaround

Transmit or receive CLOCK must not be gated (by the mean of CKO field) when START

condition is performed on a generated frame synchro.

Corrupted read in flash may happen after fuses write or erase operations (FLASHC

LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands)

After a flash fuse write or erase operation (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB,

EAGPF commands), reading (data read or code fetch) in flash may fail. This may lead to an

exception or to other errors derived from this corrupted read access.

Fix/Workaround

Before the flash fuse write or erase operation, enable the flash high speed mode (FLASHC

HSEN command). The flash fuse write or erase operations (FLASHC LP, UP, WGPB,

EGPB, SSB, PGPFB, EAGPF commands) must be issued from RAM or through the EBI.

相關(guān)PDF資料	PDF描述
S80C154-20	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44
S83C154DCXXX-12	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
S83C154DXXX-12	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
SC80C52XXX-12SV	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40
MR80C52CXXX-12/883:D	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C54	制造商:INTEL 制造商全稱:Intel Corporation 功能描述:CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
S80C54-1	制造商:INTEL 制造商全稱:Intel Corporation 功能描述:CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
S80C54-2	制造商:INTEL 制造商全稱:Intel Corporation 功能描述:CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
S80C54-20	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C54-24	制造商:INTEL 制造商全稱:Intel Corporation 功能描述:CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

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