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您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄25635 > S80C52CXXX-16 (ATMEL CORP) 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44 PDF資料下載

型號(hào)：	S80C52CXXX-16
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁(yè)數(shù)：	161/1021頁(yè)
文件大小：	15196K
代理商：	S80C52CXXX-16

32072H–AVR32–10/2012

AT32UC3A3

The clock for the SDRAMC bus interface (CLK_SDRAMC) is generated by the Power Manager.

This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to

disable the SDRAMC before disabling the clock, to avoid freezing the SDRAMC in an undefined

Interrupts

The SDRAMC interrupt request line is connected to the interrupt controller. Using the SDRAMC

interrupt requires the interrupt controller to be programmed first.

Functional Description

SDRAM Device Initialization

The initialization sequence is generated by software. The SDRAM devices are initialized by the

following sequence:

SDRAM features must be defined in the CR register by writing the following fields with

the desired value: asynchronous timings (TXSR, TRAS, TRCD, TRP, TRC, and TWR),

Number of Columns (NC), Number of Rows (NR), Number of Banks (NB), CAS Latency

(CAS), and the Data Bus Width (DBW).

For mobile SDRAM devices, Temperature Compensated Self Refresh (TCSR), Drive

Strength (DS) and Partial Array Self Refresh (PASR) fields must be defined in the Low

Power Register (LPR).

The Memory Device Type field must be defined in the Memory Device Register

A No Operation (NOP) command must be issued to the SDRAM devices to start the

SDRAM clock. The user must write the value one to the Command Mode field in the

SDRAMC Mode Register (MR.MODE) and perform a write access to any SDRAM

A minimum pause of 200s is provided to precede any signal toggle.

An All Banks Precharge command must be issued to the SDRAM devices. The user

must write the value two to the MR.MODE field and perform a write access to any

SDRAM address.

Eight Auto Refresh commands are provided. The user must write the value four to the

MR.MODE field and performs a write access to any SDRAM location eight times.

A Load Mode Register command must be issued to program the parameters of the

SDRAM devices in its Mode Register, in particular CAS latency, burst type, and burst

length. The user must write the value three to the MR.MODE field and perform a write

access to the SDRAM. The write address must be chosen so that BA[1:0] are set to

zero. See Section 16.8.1 for details about Load Mode Register command.

For mobile SDRAM initialization, an Extended Load Mode Register command must be

issued to program the SDRAM devices parameters (TCSR, PASR, DS). The user must

write the value five to the MR.MODE field and perform a write access to the SDRAM.

The write address must be chosen so that BA[1] or BA[0] are equal to one. See Section

16.8.1 for details about Extended Load Mode Register command.

10. The user must go into Normal Mode, writing the value 0 to the MR.MODE field and per-

forming a write access at any location in the SDRAM.

11. Write the refresh rate into the Refresh Timer Count field in the Refresh Timer Register

(TR.COUNT). The refresh rate is the delay between two successive refresh cycles. The

SDRAM device requires a refresh every 15.625s or 7.81s. With a 100MHz fre-

相關(guān)PDF資料	PDF描述
S80C52CXXX-25SHXXX	8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQCC44
S80C32-20SHXXX:D	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44
S80C32-20SHXXX:R	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44
S80C32-40SHXXX:RD	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
S80C52XXX-12:RD	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C52T-12	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-20	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-25	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-30	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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