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型號(hào)：	S80C52CXXX-16
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁(yè)數(shù)：	1000/1021頁(yè)
文件大?。?/td>	15196K
代理商：	S80C52CXXX-16

32072H–AVR32–10/2012

AT32UC3A3

Interrupt Priority Register (IPR). The GrpReq inputs are then masked by the mask bits from the

CPU status register. Any interrupt group that has a pending interrupt of a priority level that is not

masked by the CPU status register, gets its corresponding ValReq line asserted.

Masking of the interrupt requests is done based on five interrupt mask bits of the CPU status

rupt Mask (GM). An interrupt request is masked if either the GM or the corresponding interrupt

level mask bit is set.

The Prioritizer hardware uses the ValReq lines and the INTLEVEL field in the IPRs to select the

pending interrupt of the highest priority. If an NMI interrupt request is pending, it automatically

gets the highest priority of any pending interrupt. If several interrupt groups of the highest pend-

ing interrupt level have pending interrupts, the interrupt group with the lowest number is

The INTLEVEL and handler autovector offset (AUTOVECTOR) of the selected interrupt are

transmitted to the CPU for interrupt handling and context switching. The CPU does not need to

know which interrupt is requesting handling, but only the level and the offset of the handler

address. The IRR registers contain the interrupt request lines of the groups and can be read via

user interface registers for checking which interrupts of the group are actually active.

The delay through the INTC from the peripheral interrupt request is set until the interrupt request

to the CPU is set is three cycles of CLK_SYNC.

Non-Maskable Interrupts

A NMI request has priority over all other interrupt requests. NMI has a dedicated exception vec-

tor address defined by the AVR32 architecture, so AUTOVECTOR is undefined when

INTLEVEL indicates that an NMI is pending.

CPU Response

When the CPU receives an interrupt request it checks if any other exceptions are pending. If no

exceptions of higher priority are pending, interrupt handling is initiated. When initiating interrupt

handling, the corresponding interrupt mask bit is set automatically for this and lower levels in sta-

tus register. E.g, if an interrupt of level 3 is approved for handling, the interrupt mask bits I3M,

I2M, I1M, and I0M are set in status register. If an interrupt of level 1 is approved, the masking

bits I1M and I0M are set in status register. The handler address is calculated by logical OR of

the AUTOVECTOR to the CPU system register Exception Vector Base Address (EVBA). The

CPU will then jump to the calculated address and start executing the interrupt handler.

Setting the interrupt mask bits prevents the interrupts from the same and lower levels to be

passed through the interrupt controller. Setting of the same level mask bit prevents also multiple

requests of the same interrupt to happen.

It is the responsibility of the handler software to clear the interrupt request that caused the inter-

rupt before returning from the interrupt handler. If the conditions that caused the interrupt are not

cleared, the interrupt request remains active.

Clearing an Interrupt Request

Clearing of the interrupt request is done by writing to registers in the corresponding peripheral

module, which then clears the corresponding NMIREQ/IREQ signal.

The recommended way of clearing an interrupt request is a store operation to the controlling

peripheral register, followed by a dummy load operation from the same register. This causes a

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S80C32-20SHXXX:D	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44
S80C32-20SHXXX:R	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44
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S80C52XXX-12:RD	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C52T-12	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-20	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-25	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-30	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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