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您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25635 > S80C52CXXX-16 (ATMEL CORP) 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44 PDF資料下載

型號(hào)：	S80C52CXXX-16
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁(yè)數(shù)：	137/1021頁(yè)
文件大?。?/td>	15196K
代理商：	S80C52CXXX-16

32072H–AVR32–10/2012

AT32UC3A3

Figure 15-24. TDF Optimization Disabled (MODE.TDFMODE = 0). TDF Wait States between Read and Write accesses on

the Same Chip Select.

External Wait

Any access can be extended by an external device using the NWAIT input signal of the SMC.

The External Wait Mode field of the MODE register (MODE.EXNWMODE) on the corresponding

chip select must be written to either two (frozen mode) or three (ready mode). When the

MODE.EXNWMODE field is written to zero (disabled), the NWAIT signal is simply ignored on

the corresponding chip select. The NWAIT signal delays the read or write operation in regards to

the read or write controlling signal, depending on the read and write modes of the corresponding

chip select.

When one of the MODE.EXNWMODE is enabled, it is mandatory to program at least one hold

cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be used in

The NWAIT signal is assumed to be a response of the external device to the read/write request

of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write

controlling signal. The assertion of the NWAIT signal outside the expected period has no impact

on SMC behavior.

When the external device asserts the NWAIT signal (active low), and after internal synchroniza-

tion of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control

signals remain unchanged. When the synchronized NWAIT signal is deasserted, the SMC com-

pletes the access, resuming the access from the point where it was stopped. See Figure 15-25

on page 202. This mode must be selected when the external device uses the NWAIT signal to

delay the access and to freeze the SMC.

Read1 controlling

Write2 controlling

Read1 hold = 1

TDFCYCLES = 5

TDFCYCLES = 5

Read to Write

4 TDF WAIT STATES

Write2 setup = 1

Write 2 cycle

(optimization disabled)

相關(guān)PDF資料	PDF描述
S80C52CXXX-25SHXXX	8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQCC44
S80C32-20SHXXX:D	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44
S80C32-20SHXXX:R	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44
S80C32-40SHXXX:RD	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
S80C52XXX-12:RD	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C52T-12	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-20	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-25	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-30	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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