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參數(shù)資料
| 型號： | S71WS512N80BFIZZ2 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和移動存儲芯片的CMOS 1.8伏特 |
| 文件頁數(shù)： | 96/142頁 |
| 文件大?。?/td> | 1996K |
| 代理商： | S71WS512N80BFIZZ2 |
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96
128Mb pSRAM
S71WS512NE0BFWZZ_00_A1 June 28, 2004
P r e l i m i n a r y
FUNCTION TRUTH TABLE (Continued)
Synchronous Operation (Burst Mode)
Notes:L = V
IL
, H = V
IH
, X can be either V
IL
or V
IH
,
High-Z = High Impedance
*1: Should not be kept this logic condition longer than 4ms.
Please contact local FUJITSU representative for the relaxation of 4ms limitation.
*2: Power Down mode can be entered from Standby state and all DQ pins are in High-Z state.
Data retention depends on the selection of Partial Size.
Refer to "Power Down" in FUNCTIONAL DESCRIPTION for the details.
*3: Valid clock edge shall be set on either positive or negative edge through CR Set. CLK must be started and
stable prior to memory access.
*4: Can be either V
IL
or V
IH
except for the case the both of OE# and WE# are V
IL
. It is prohibited to bring the
both of OE# and WE# to V
IL
*5: When device is operating in "WE# Single Clock Pulse Control" mode, WE# is don’t care once write operation
is determined by WE# Low Pulse at the beginnig of write access together with address latching. Write
suspend feature is not supported in "WE# Single Clock Pulse Control" mode
*6: Can be either V
IL
or V
IH
but must be valid before Read or Write is determined. And once UB# and LB#
inputs are determined, they must not be changed until the end of burst.
*7: Once valid address is determined, input address must not be changed during ADV#=L.
*8: If OE#=L, output is either Invalid or High-Z depending on the level of UB# and LB# input. If WE#=L,
Input is Invalid. If OE#=WE#=H, output is High-Z.
*9: Output is either Valid or High-Z depending on the level of UB# and LB# input.
*10: Input is either Valid or Invalid depending on the level of UB# and LB# input.
*11: Output is either High-Z or Invalid depending on the level of OE# and WE# input.
*12: Keep the level from previous cycle except for suspending on last data. Refere to "WAIT# Output Function"
in FUNCTIONAL DESCRIPTION for the details.
*13: WAIT# output is driven in High level during write operation.
= valid edge,
= positive edge of Low pulse,
Mode
Note
CE2
CE#1
CLK
ADV#
WE#
OE#
LB#
UB#
A22-0
DQ8-1
DQ16-9
WAIT#
Standby
(Deselect)
H
H
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
Start
Address Latch
*1
L
*3
*4
X
*4
X
*6
X
*6
X
*7
Valid
*8
High-Z
*8
High-Z
*11
High-Z
Advance
Burst Read to
Next Address
*1
*3
H
H
L
X
*9
Output
Valid
*9
Output
Valid
Output
Valid
Burst Read
Suspend
*1
*3
H
High-Z
High-Z
*12
High
Advance
Burst Write to
Next Address
*1
*3
*5
L
H
*10
Input
Valid
*10
Input
Valid
*13
High
Burst Write
Suspend
*1
*3
*5
H
Input
Invalid
Input
Invalid
*12
High
Terminate
Burst Read
X
H
X
High-Z
High-Z
High-Z
Terminate
Burst Write
X
X
H
High-Z
High-Z
High-Z
Power Down
*2
L
X
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
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| S71WS512N80BFIZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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| S71WS512N80BFWZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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