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參數(shù)資料
| 型號： | S71WS512N80BAWZZ3 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| 中文描述： | 堆疊式多芯片產品（MCP）的閃存和移動存儲芯片的CMOS 1.8伏特 |
| 文件頁數(shù)： | 53/142頁 |
| 文件大?。?/td> | 1996K |
| 代理商： | S71WS512N80BAWZZ3 |
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June 28, 2004 S71WS512NE0BFWZZ_00_A1
S29WSxxxN MirrorBit Flash Family For Multi-chip Products (MCP)
53
A d v a n c e I n f o r m a t i o n
case, the RDY pin will always indicate that the device is ready to handle a new
transaction when low.
Configuration Register
Table 16
shows the address bits that determine the configuration register settings
for various device functions.
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read
mode. Address bits are don’t cares for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the bank to which the sys-
tem was writing to the read mode. Once erasure begins, however, the device
ignores reset commands until the operation is complete.
Table 16. Configuration Register
CR BIt
Function
Set Device
Read Mode
Settings (Binary)
CR15
0 = Synchronous Read (Burst Mode) Enabled
1 = Asynchronous Mode (default)
0 = No extra boundary crossing latency
1 = With extra boundary crossing latency (default)
000 = Data is valid on the 2nd active CLK edge after addresses are latched
001 = Data is valid on the 3rd active CLK edge after addresses are latched
010 = Data is valid on the 4th active CLK edge after addresses are latched
011 = Data is valid on the 5th active CLK edge after addresses are latched
100 = Data is valid on the 6th active CLK edge after addresses are latched
101 = Data is valid on the 7th active CLK edge after addresses are latched (default)
110 = Reserved
111 = Reserved
0 = RDY signal is active low
1 = RDY signal is active high (default)
CR14
Boundary
Crossing
CR13
Programmable
Wait State
CR12
CR11
CR10
RDY Polarity
CR9
Set Internal
Clock
Frequency
0 = Reserved for Future Use
1 = Internal clock switches at full frequency of the external clock (default)
CR8
RDY
0 = RDY active one clock cycle before data
1 = RDY active with data (default)
0 = Reserved for Future Use
1 = Sequential Burst Order (default)
0 = Burst starts and data is output on the falling edge of CLK
1 = Burst starts and data is output on the rising edge of CLK (default)
0 = No Wrap Around Burst
1 = Wrap Around Burst (default)
CR7
Burst
Sequence
CR6
Clock
CR3
Burst Wrap
Around
CR2
Burst Length
000 = Continuous (default)
010 = 8-Word Linear Burst
011 = 16-Word Linear Burst
100 = 32-Word Linear Burst
(All other bit settings are reserved)
CR1
CR0
Notes:
Device will be in the default state upon power-up or hardware reset.
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相關代理商/技術參數(shù) |
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| S71WS512N80BFEZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFIZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFIZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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