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參數(shù)資料
| 型號(hào)： | S71WS512N80BAIZZ2 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和移動(dòng)存儲(chǔ)芯片的CMOS 1.8伏特 |
| 文件頁(yè)數(shù)： | 23/142頁(yè) |
| 文件大?。?/td> | 1996K |
| 代理商： | S71WS512N80BAIZZ2 |
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June 28, 2004 S71WS512NE0BFWZZ_00_A1
S29WSxxxN MirrorBit Flash Family For Multi-chip Products (MCP)
23
A d v a n c e I n f o r m a t i o n
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is com-
posed of latches that store the commands, along with the address and data
information needed to execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the
function of the device.
Table 2
lists the device bus operations, the inputs and con-
trol levels they require, and the resulting output. The following subsections
describe each of these operations in further detail.
Legend:
L = Logic 0, H = Logic 1, X = Don’t Care.
Note:
Default active edge of CLK is the rising edge.
Requirements for Asynchronous Read Operation (Non-
Burst)
To read data from the memory array, the system must first assert a valid address
on A23–A0 for WS256N , while driving AVD# and CE# to V
IL
. WE# should remain
at V
IH
. The rising edge of AVD# latches the address. The data will appear on
DQ15–DQ0. Since the memory array is divided into sixteen banks, each bank re-
mains enabled for read access until the command register contents are altered.
Address access time (t
ACC
) is equal to the delay from stable addresses to valid
output data. The chip enable access time (t
CE
) is the delay from the stable ad-
dresses and stable CE# to valid data at the outputs. The output enable access
time (t
OE
) is the delay from the falling edge of OE# to valid data at the output.
The internal state machine is set for reading array data in asynchronous mode
upon device power-up, or after a hardware reset. This ensures that no spurious
alteration of the memory content occurs during the power transition.
Table 2. Device Bus Operations
Operation
Asynchronous Read - Addresses Latched
Asynchronous Read - Addresses Steady State
Asynchronous Write
Synchronous Write
Standby (CE#)
Hardware Reset
CE#
L
L
L
L
H
X
OE#
L
L
H
H
X
X
WE#
H
H
L
L
X
X
Addresses
Addr In
Addr In
Addr In
Addr In
X
X
DQ15–0
I/O
I/O
I/O
I/O
HIGH Z
HIGH Z
RESET#
H
H
H
H
H
L
CLK
(See
Note
)
X
X
X
AVD#
L
L
X
X
X
X
Burst Read Operations (Synchronous)
Load Starting Burst Address
Advance Burst to next address with
appropriate Data presented on the Data Bus
Terminate current Burst read cycle
Terminate current Burst read cycle via RESET#
Terminate current Burst read cycle and start
new Burst read cycle
L
X
H
Addr In
X
H
L
L
H
X
Burst
Data Out
HIGH Z
HIGH Z
H
H
H
X
X
X
H
H
X
X
H
L
X
X
X
L
X
H
Addr In
I/O
H
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| S71WS512N80BAWZZ2 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71WS512N80BAIZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAWZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAWZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAWZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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