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參數(shù)資料
| 型號： | S71GL064A80BFW0B3 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和RAM |
| 文件頁數(shù)： | 39/102頁 |
| 文件大?。?/td> | 1606K |
| 代理商： | S71GL064A80BFW0B3 |
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March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
39
A d v a n c e I n f o r m a t i o n
Low V
CC
W rite I nhibit
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This pro-
tects data during V
CC
power-up and power-down. The command register and all
internal program/erase circuits are disabled, and the device resets to the read
mode. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system
must provide the proper signals to the control pins to prevent unintentional writes
when V
CC
is greater than V
LKO
.
W rite Pulse “ Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
Logical I nhibit
Write cycles are inhibited by holding any one of OE# = V
IL
, CE# = V
IH
or WE# =
V
IH
. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
logical one.
Pow er-Up W rite I nhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automatically
reset to the read mode on power-up.
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| S71GL064A80BFW0F3 | Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71GL064A80BFW0F0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
| S71GL064A80BFW0F2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
| S71GL064A80BFW0F3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
| S71GL064AA0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM |
| S71GL064AA0-0K | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM |
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