參數(shù)資料
型號： S71GL064A40BFI0B3
廠商： Spansion Inc.
英文描述： Stacked Multi-Chip Product (MCP) Flash Memory and RAM
中文描述： 堆疊式多芯片產(chǎn)品（MCP）的閃存和RAM
文件頁數(shù)： 67/102頁
文件大?。?/td> 1606K
代理商： S71GL064A40BFI0B3
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
67
Advance
Informatio n
AC Characteristics
Read-Only Operations-S29GL064A only
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 24 for test specifications.
Read-Only Operations-S29GL032A only
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 24 for test specifications.
Parameter
Description
Test Setup
Speed Options
Unit
JEDEC
Std.
90
10
11
tAVAV
tRC
Read Cycle Time (Note 1)
Min
90
100
110
ns
tAVQV
tACC
Address to Output Delay
CE#, OE# = VIL
Max
90
100
110
ns
tELQV
tCE
Chip Enable to Output Delay
OE# = VIL
Max
90
100
110
ns
tPACC
Page Access Time
Max
25
30
ns
tGLQV
tOE
Output Enable to Output Delay
Max
25
30
ns
tEHQZ
tDF
Chip Enable to Output High Z (Note 1)
Max
16
ns
tGHQZ
tDF
Output Enable to Output High Z (Note 1)
Max
16
ns
tAXQX
tOH
Output Hold Time From Addresses, CE# or OE#, Whichever Occurs
First
Min
0
ns
tOEH
Output Enable Hold Time
(Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
Parameter
Description
Test Setup
Speed Options
Unit
JEDEC
Std.
90
10
11
tAVAV
tRC
Read Cycle Time (Note 1)
Min
90
100
110
ns
tAVQV
tACC
Address to Output Delay
CE#, OE# = VIL
Max
90
100
110
ns
tELQV
tCE
Chip Enable to Output Delay
OE# = VIL
Max
90
100
110
ns
tPACC
Page Access Time
Max
25
30
ns
tGLQV
tOE
Output Enable to Output Delay
Max
25
30
ns
tEHQZ
tDF
Chip Enable to Output High Z (Note 1)
Max
16
ns
tGHQZ
tDF
Output Enable to Output High Z (Note 1)
Max
16
ns
tAXQX
tOH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
Min
0
ns
tOEH
Output Enable Hold Time (Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
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參數(shù)描述
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