
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
Page 9
S4402/S4403
BiCMOS PLL CLOCK GENERATOR
Table 4. AC Specifications
Symbol
Description
Min
Max
Min
Max
Units
f
VCO
VCO Frequency
160
266
160
320
MHz
REF
REFCLK Frequency
10
66
10
80
MHz
MPW
REF
REFCLK Minimum Pulse Width
7.0
6.0
ns
t
PE
Phase Error between REFCLK and FBCLK
-1.0
0
-1.0
0
ns
t
PED
Phase Error Difference from Part to Part
1
0
750
0
750
ps
t
SKEW
Output Skew
2
0
400
0
400
ps
t
DC
Output Duty Cycle
3
45
55
45
55
%
f
FOUT
FOUT Frequency
4
20
66
20
80
MHz
f
HFOUT
HFOUT Frequency
4
10
33
10
40
MHz
f
2XFOUT
2XFOUT Frequency
4
40
66
40
80
MHz
t
PS
Nominal Phase Shift Increment
3.75
6.25
3.125
6.25
ns
t
PSJ
Phase Shift Variation
5
-250
+250
-250
+250
ps
t
OFD
Tpd OUTEN0–2 to FOUTs, Disable
2
7
2
7
ns
t
OFE
Tpd OUTEN0–2 to FOUTs, Enable
2
7
2
7
ns
t
IRF
Input Rise/Fall Time
1
3
1
3
ns
t
ORF
FOUT Rise/Fall Time
6
0.5
1.5
0.5
1.5
ns
t
LOCK
Loop Acquisition Time
7
5
5
ms
t
j
1. Difference in phase error between two parts at the same voltage, temperature and frequency.
2. Output skew guaranteed for equal loading at each output.
3. Outputs loaded with 35pF, measured at 1.5V.
4. C
= 35 pF.
5. All phase shift increments and variation are measured relative to FOUT0 at 1.5V.
6. With 35 pF output loading (0.8 V to 2.0 V transition).
7. Depends on loop filter chosen. (Number given is for example filter.)
8. Clock period jitter with all FOUT outputs operating at 66 MHz and loaded with 25pF using loop filter
shown. Parameter guaranteed, but not tested.
Clock Stability
8
500
500
ps
S4402/3-66
S4402/3-80
REFCLK
REF
MPW
FBCLK
FOUT0–3
OUTEN0–2
t
PE
REF
MPW
HFOUT, X2FOUT
t
SKEW
t
SKEW
t
PE
t
OFD
t
OFE
Output Valid
Disabled
HFOUT, X2FOUT
FOUT0–3
Figure 5. Timing Waveforms