參數(shù)資料
型號(hào): S4403
廠商: Applied Micro Circuits Corp.
英文描述: BiCMOS PLL Clock Generator(能產(chǎn)生6個(gè)時(shí)鐘輸出的BiCMOS鎖相環(huán)時(shí)鐘發(fā)生器)
中文描述: BiCMOS工藝PLL時(shí)鐘發(fā)生器(能產(chǎn)生6個(gè)時(shí)鐘輸出的BiCMOS工藝鎖相環(huán)時(shí)鐘發(fā)生器)
文件頁(yè)數(shù): 5/13頁(yè)
文件大?。?/td> 154K
代理商: S4403
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
Page 5
BiCMOS PLL CLOCK GENERATOR
Table 3. Output Select Matrix
Configuration
Number
Select Pins
Output Fed
to FBCLK
Output Phase Relationships
÷
4
X2FOUT
÷
8
PHSEL1 PHSEL0
FOUT0
FOUT1
FOUT2
FOUT3
HFOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
FOUT0–FOUT3
HFOUT
X2FOUT (
÷
8)
FOUT0
FOUT1
FOUT2
FOUT3
HFOUT
X2FOUT (
÷
8)
FOUT0
FOUT1
FOUT2
FOUT3
HFOUT
X2FOUT (
÷
8)
FOUT0
FOUT1
FOUT2
FOUT3
HFOUT
X2FOUT (
÷
8)
0
0
0
0
0/2
0
0/4
0/2
–Q/2
–2Q/2
–3Q/2
0
0/4
0/2
t/2
–t/2
–Q/2
0
0/4
0/2
–t/2
–2t/2
–3t/2
0
0/4
0
2(0)
4(0)
0
2(0)
2(–Q)
2(–2Q)
2(–3Q)
4(0)
0
2(0)
2(t)
2(–t)
2(–Q)
4(0)
0
2(0)
2(–t)
2(–2t)
2(–3t)
4(0)
0
2(0)
0/2
0
–Q
–2Q
–3Q
2(0)
0/2
0
t
–t
–Q
2(0)
0/2
0
–t
–2t
–3t
2(0)
0/2
2(0)
0/2
Q
0
–Q
–2Q
2(Q)
Q/2
–t
0
–2t
–Q–t
2(–t)
–t/2
t
0
–t
–2t
2(t)
t/2
2(0)
0/2
2Q
Q
0
–Q
2(2Q)
2Q/2
t
2t
0
–Q+t
2(t)
t/2
2t
t
0
–t
2(2t)
2t/2
2(0)
0/2
3Q
2Q
Q
0
2(3Q)
3Q/2
Q
Q+t
Q–t
0
2(Q)
Q/2
3t
2t
t
0
2(3t)
3t/2
2(0)
0
–Q
–2Q
–3Q
2(0)
0
t
–t
–Q
2(0)
0
–t
–2t
–3t
2(0)
Notes: 1. “0” implies the output is aligned with REFCLK.
2. “t” implies the output lags REFCLK by a minimum phase delay.
3. “Q” implies the output lags REFCLK by 90
°
of phase
4. “–t” implies the output leads REFCLK by a minimum phase delay.
5. “–Q” implies the output leads REFCLK by 90
°
of phase.
6. “2( )” implies the output is at twice the frequency of REFCLK.
S4402/S4403
0
t
–t
2t
REFCLK
0
Q
2Q
–Q
REFCLK
2(0)
0/2
0/4
4(0)
REFCLK
0° 90°180°
Table
entry
Table
entry
Table
entry
Waveform
Waveform
Waveform
–t
t 2t
–90°
Legend
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