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參數(shù)資料
| 型號(hào)： | S3P7559-AT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDIP64 |
| 封裝： | 0.750 INCH, SDIP-64 |
| 文件頁(yè)數(shù)： | 69/197頁(yè) |
| 文件大?。?/td> | 1181K |
| 代理商： | S3P7559-AT |
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S3C7559/P7559
SERIAL I/O INTERFACE
13-3
SERIAL I/O MODE REGISTER (SMOD)
The serial I/O mode register, SMOD, is an 8-bit register that specifies the operation mode of the serial interface.
Its reset value is logic zero. SMOD is organized in two 4-bit registers, as follows:
FE0H
SMOD.3
SMOD.2
SMOD.1
SMOD.0
FE1H
SMOD.7
SMOD.6
SMOD.5
0
SMOD register settings enable you to select either MSB-first or LSB-first serial transmission, and to operate in
transmit-and-receive mode or receive-only mode.
SMOD is a write-only register and can be addressed only by 8-bit RAM control instructions. One exception to this
is SMOD.3, which can be written by a 1-bit RAM control instruction. When SMOD.3 is set to 1, the contents of
the serial interface interrupt request flag, IRQS, and the 3-bit serial clock counter are cleared, and SIO
operations are initiated. When the SIO transmission starts, SMOD.3 is cleared to logic zero.
Table 13-1. SIO Mode Register (SMOD) Organization
SMOD.0
0
Most significant bit (MSB) is transmitted first
1
Least significant bit (LSB) is transmitted first
SMOD.1
0
Receive-only mode; output buffer is off
1
Transmit-and-receive mode
SMOD.2
0
Disable the data shifter and clock counter; retain contents of IRQS flag when serial
transmission is halted
1
Enable the data shifter and clock counter; set IRQS flag to "1" when serial
transmission is halted
SMOD.3
1
Clear IRQS flag and 3-bit clock counter to "0"; initiate transmission and then reset
this bit to logic zero
SMOD.4
0
Bit not used; value is always "0"
SMOD.7
SMOD.6
SMOD.5
Clock Selection
R/W Status of SBUF
0
External clock at
SCK pin
SBUF is enabled when SIO operation
is halted or when
SCK goes high.
0
1
Use TOL0 clock from TC0
0
1
x
CPU clock: fxx/4, fxx/8,
fxx/64
Enable SBUF read/write
1
0
3.49 kHz clock: fxx/210
SBUF is enabled when SIO operation
is halted or when
SCK goes high.
1
223.7 kHz clock: fxx/24
NOTES:
1.
'fxx' = system clock; 'x' means 'don't care.'
2.
kHz frequency ratings assume a system clock (fxx) running at 3.579545 MHz.
3.
The SIO clock selector circuit cannot select a fxx/24 clock if the CPU clock is fxx/64
.
4.
When a internal clock is selected as a clock source for the serial I/O interface (by setting other values than "000" in
SMOD.7–SMOD.5), the clock can be output from
SCK pin.
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