
POWER-DOWN
S3C7559/P7559
8-6
PORT PIN CONFIGURATION FOR POWER-DOWN
The following method describes how to configure I/O port pins to reduce power consumption during power-down
modes (stop, idle):
Condition 1:
If the microcontroller is not configured to an external device:
1.
Connect unused port pins according to the information in Table 8-2.
2.
Disable all pull-up resistors for output pins by making the appropriate modifications to the pull-up resistor
mode register, PUMOD. Reason: If output goes low when the pull-up resistor is enabled, there may be un-
expected surges of current through the pull-up.
3.
Disable pull-up resistors for input pins configured to V
DD or VSS levels in order to check the current input
option. Reason: If the input level of a port pin is set to V
SS when a pull-up resistor is enabled, it will draw an
unnecessarily large current.
Condition 2:
If the microcontroller is configured to an external device and the external device's V
DD source is
turned off in power-down mode.
1.
Connect unused port pins according to the information in Table 8-2.
2.
Disable the pull-up resistors of output pins by making the appropriate modifications to the pull-up resistor
mode register, PUMOD. Reason: If output goes low when the pull-up resistor is enabled, there may be un-
expected surges of current through the pull-up.
3.
Disable pull-up resistors for input pins configured to V
DD or VSS levels in order to check the current input
option. Reason: If the input level of a port pin is set to V
SS when a pull-up resistor is enabled, it will draw an
unnecessarily large current.
4.
Disable the pull-up resistors of input pins connected to the external device by making the necessary modi-
fications to the PUMOD register.
5.
Configure the output pins that are connected to the external device to low level. Reason: When the external
device's V
DD source is turned off, and if the microcontroller's output pins are set to high level, VDD – 0.7 V is
supplied to the V
DD of the external device through its input pin. This causes the device to operate at the level
V
DD – 0.7 V. In this case, total current consumption would not be reduced.
6.
Determine the correct output pin state necessary to block current pass in according with the external tran-
sistors (PNP, NPN).