參數(shù)資料
型號: S3056
廠商: Applied Micro Circuits Corp.
英文描述: Multi-Rate SONET/SDH Clock Recovery Unit(多速率SONET/SDH時鐘恢復單元)
中文描述: 多速率SONET / SDH時鐘恢復單元(多速率SONET / SDH的時鐘恢復單元)
文件頁數(shù): 5/17頁
文件大小: 152K
代理商: S3056
5
S3056
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
October 31, 2000 / Revision J
FIBRE CHANNEL
JITTER CHARACTERISTICS
Performance
The S3056 PLL complies with the jitter specifications
proposed for Fibre Channel equipment defined by the
fibre channel methodology for Jitter specification.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to
peak amplitude of sinusoidal jitter applied on the
input signal that causes an equivalent 1 dB opti-
cal/electrical power penalty. Fibre Channel input
jitter tolerance requirements are shown in
Table 3.
SYSTEM
STORAGE
DISK DRIVE
SERDES
SERDES
BACKPLANE
PBC
REPEAETERS
CABLES
CONNECTORS
Componet Receiver Node =
α
R
SYSTEM
HOST ADAPTOR
α
T
= Component Transmitter Node
Figure 5. Fibre Channel System Node Definition
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Table 3. Input Jitter Tolerance Specification at node
α
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Table 4. Total Jitter Generation Specification at node
α
T
Jitter Generation
The jitter of the serial clock and serial data outputs
shall not exceed the value specified in Table 4 when
a serial data input with no jitter is presented to the
serial data inputs.
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