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參數(shù)資料
| 型號(hào)： | S3051 |
| 廠商： | Applied Micro Circuits Corp. |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | 2.5 Gbps Limiting Amplifier(用于光纖接收的高增益寬帶寬的2.5 Gbps限幅放大器) |
| 中文描述： | 2.5 Gbps的限幅放大器（用于光纖接收的高增益寬帶寬的2.5 Gbps的限幅放大器） |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大小： | 220K |
| 代理商： | S3051 |
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S3051
2.5 GBPS LIMITING AMPLIFIER
July 14, 1999 / Revision B
DETAILED DESCRIPTION
The S3051 is an integrated limiting amplifier in-
tended for high-frequency fiber-optic applications.
The circuit connects to typical transimpedance am-
plifiers found within a fiber-optic link. The linear
signal output from a transimpedance amplifier can
contain significant amounts of noise, and may vary
in amplitude over time. The S3051 limiting amplifier
quantizes the signal, and outputs a voltage limited
waveform over a 38 dB input dynamic range.
At low signal levels, below 12 mVp-p, the circuit be-
haves as a linear amplifier. At higher levels the
device becomes a limiting amplifier.
Figure 2. Functional Block Diagram
DOUT–
DOUT+
DIN–
DIN+
V–
REF
V+
REF
50
11
10
9
8
7
6
5
4
3
12
2
1
16
15
14
13
NC
VCC(OB)
VCC(GS1,SS2)
GND(OB)
GND(OB)
GND(OB)
GND(OB)
GND(GS1,GS2)
GND(GS1,GS2)
5k
5k
VCC(GS1,GS2)
VCC= +5V
NC ..... No Connect
GS1
GS2
OB
110pF
110pF
50
5k
5k
The referred wideband input noise (160
μ
Vrms) al-
lows for a less than 1E-9 Bit Error Rate for inputs
down to 2 mVp-p.
The S3051 is designed to allow adjustment of the
DC offset between the DIN+ and DIN– inputs. V
+REF
can be used as a reference from which the required
offset can be subtracted to set the DC bias level at
DIN–. Similarly, V
–REF
can be used to set the DC
bias level at DIN+. (See Application Information).
If no adjustment is made to the input DC bias level,
two resistors can be connected in a negative feed-
back configuration in order to cancel any DC offset
at the input. This will minimize the pulse width distor-
tion. (See separate S3051 Limiting Amplifier
Application document.)
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