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參數(shù)資料
| 型號： | S3042 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH/ATM OC-48 1：8 Receiver(帶片上高頻鎖相環(huán)的1：8 SONET/SDH接收器（集成SONET OC-48接口器件）) |
| 中文描述： | MUX/DEMUX, PQFP52 |
| 封裝： | 14 X 14 MM, 2 MM HEIGHT, PLASTIC, QFP-52 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 147K |
| 代理商： | S3042 |
14
S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
June 24, 1999 / Revision E
RECEIVER FRAMING
Figure 10 shows a typical reframe sequence in
which a byte realignment is made. The frame and
byte boundary detection is enabled by the rising
edge of OOF. The byte alignment is made during the
A1 data sequence, resulting in correct byte align-
ment on the outgoing data bus (POUT[7:0]). Frame
boundary is recognized upon receipt of the first A2
byte, and is reported via the frame pulse being set
high for one POCLK cycle concurrent with the third
A2 byte.
The frame and byte boundary detection block is acti-
vated by the rising edge of OOF, and stays active until
the first FP pulse.
Figure 11 shows the frame and byte boundary detection
activation by a rising edge of OOF, and deactivated by
the first FP pulse.
Figure 12 shows the frame and byte boundary detec-
tion activation by a rising edge of FRAMEN, and
deactivated by the FRAMEN input.
Figure 12 also shows the frame and byte boundary
detection activation by a rising edge on FRAMEN,
and deactivation by the first FP pulse.
Figure 10. Frame and Byte Detection
Invalid Data
Valid Data
A1
A1
A1
A1
A2
A2
A2 (28H)
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