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參數(shù)資料
| 型號(hào)： | S3031B |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | E4/STM-1/OC-3 ATM TRANSCEIVER |
| 中文描述： | TRANSCEIVER, PQFP100 |
| 封裝： | 0.65 MM PITCH, HEAT SINK, PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 4/26頁(yè) |
| 文件大?。?/td> | 262K |
| 代理商： | S3031B |
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4
S3031B
E4/STM-1/OC-3 ATM TRANSCEIVER
August 19, 1999 / Revision D
Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 9 is
comprised of two 4-bit registers. The first register latches
the data from the PIN[3:0] bus on the rising edge of
REFCLK. The second register is a parallel loadable
shift register which takes its parallel input from the first
register.
The parallel data transfer between registers is accom-
plished on the falling edge of REFCLK. The serial data
is shifted out at the serial bit rate to the CMI encoder.
CMI Encoding
Coded Mark Inversion format (CMI) ensures at least
one data transition per 1.5 bit periods, thus aiding
the clock recovery process. Zeros are represented
by a Low state for one half a bit period, followed by a
High state for the rest of that bit period. Ones are
represented by a steady Low or High state for a full
bit period. The state of the ones bit period alternates
at each occurrence of a one. Figure 4 shows an
example of CMI-encoded data. The STS-3 electrical
interface and the E4 interface are specified to have
CMI-encoded data.
The CMI encoder on the S3031B accepts serial data
from TSDATIP/N at 139.264 or 155.52 Mb/s. The
data is then encoded into CMI format, and the result
is shifted out with transitions at twice the basic data
rate. The CMISEL input controls whether the CMI en-
coder is in the data path. A CMI code violation can be
inserted for diagnostic purposes by activating the
DLCV input. The DLCV input is sampled on every
cycle of the serial clock to allow the single or multiple
line code violations to be inserted. This violation is
either an inverted zero code or an inversion of the
alternating ones logic level, depending on the state of
the data. Subsequent one codes take into account the
induced violation to avoid error multiplication.
Figure 5. Jitter Generation Specifications
Compliant to G.823 and G.825
Figure 6. S3031B Maximum Allowable Input Jitter
f1
STM-1
500
f1(Hz)
E4
1. UI rms
2. UI p–p
200
65
f2(kHz)
10
1.3
f3(MHz)
3.5
1.5
(2)
1.5
(2)
A1
0.15
(2)
0.075
(2)
OC-3
—
—
—
0.01
(1)
0.01
(1)
A2
A1
A2
f2
f3
500Hz
STM-1
65
f2(kHz)
—
E4
10
1. UI rms
2. UI p–p
1.45
(2)
1.45
(2)
A1
0.10
(2)
0.025
(2)
OC-3
0.005
(1)
0.005
(1)
A2
A1
A2
f2
1.3 MHz
225 kHz
Slope = +20 dB/decade
Jitter Generation
Jitter Generation is defined as the amount of jitter at
the OC-3 or E-4 output of equipment. Jitter genera-
tion for OC-3 shall not exceed 0.01 UI rms when
measured using a highpass filter with a 12 kHz cutoff
frequency.
For STM-1 and E4, the jitter generated shall not ex-
ceed the specifications shown in Figure 5.
In order to meet the SONET, STM-1 E4 jitter specifica-
tions as shown in Figure 5, the TSDATIP/N serial data
input must meet the jitter characteristics as shown in
Figure 6.
Figure 4. CMI Encoded Data
A2
A1
t
0
0
1
0
1
1
1
0
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