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參數(shù)資料
| 型號： | S3031 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | E4/STM-1/OC-3 ATM TRANSCEIVER |
| 中文描述： | TRANSCEIVER, PQFP80 |
| 封裝： | 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 8/26頁 |
| 文件大?。?/td> | 262K |
| 代理商： | S3031 |
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8
S3031B
E4/STM-1/OC-3 ATM TRANSCEIVER
August 19, 1999 / Revision D
Reference Clock Input
The reference clock input seen in Figure 9 provides
backup reference clock signals to the clock recovery
block when the clock recovery block detects a loss of
signal condition. It contains a counter that divides the
clock output from the clock recovery block down to
the same frequency as the Reference Clock
(REFCLK).
In NRZ mode, a logic Low level on the LOSOPT input
will cause the PLL to change its reference to the
reference clock. This pin should be driven by a PECL
compatible level signal detect signal from the fiber
optic receiver.
Serial Clock Output to Data Output Timing
The serial data is clocked out on the falling edge of
RSCLKOP. (See Figure 11.) This timing is valid in
both NRZ and CMI modes.
Serial to Parallel Converter
The Serial to Parallel Converter consists of two 4-bit
registers. The first is a serial-in, parallel-out shift regis-
ter, which performs serial to parallel conversion clocked
by the clock recovery block. The second is the output
holding register. On the falling edge of the free running
POCLK, the data in the serial-in, parallel-out register is
transferred to the output holding register which drives
POUT[3:0].
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to peak
amplitude of sinusoidal jitter applied on the input signal
that causes an equivalent 1 dB optical/electrical power
penalty. OC-3 and E-4 input jitter tolerance require-
ments are shown in Figure 12.
The S3031B PLL complies with the minimum jitter tol-
erance for clock recovery proposed for SONET/SDH
equipment defined by the Bellcore TA-NWT-000253
standard when used as shown in Figure 12. The
S3031B PLL also complies with the minimum jitter
tolerance for clock recovery as defined in the ITU-T E4
specification when used as shown in Figure 19.
f9
OC-3
10
f9
(Hz)
E4
TBD
30
f0
(Hz)
TBD
300
f1
(Hz)
200
6.5
f2
(kHz)
0.5
65
f3
(kHz)
10
—
f4
(MHz)
3.5
15
A2
15
1.5
A3
1.5
0.15
STM-1 (Optical) 0.125 19.3
STM-1 (Electrical) 0.125 19.3
500
6.5
65
1.3
39
1
39
1
1.5 0.15
500
6.5
65
1.3
1.5
0.15
A4
0.075
A2
A3
A4
f0
f1
f2
f3
f4
Sinusoidal
Input Jitter
Amplitude
(UI p-p)
Figure 12. Clock Recovery Jitter Tolerance
Compliant to G.823 and G.825
maximum
cable loss
nominal value
Tolerance range
“no transition condition” or “transition
condition” may be declared
“transition condition”
must be declared
“no transition condition”
must be declared
Level below Nominal
The signal level 17 is (maximum cable loss +3)
dB below nominal.
The signal level 35 is greater than the maximum
expected cross-talk level.
3 dB
17
35
Figure 10. Criteria for Determination of Transition
Conditions. Compliant to G.775.
RSDATOP
RSCLKOP/N
tPSER
Figure 11. S3031B Clock to Data Timing
Note:
1. Only tested to 20 due to test equipment limitation.
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| S3031B | E4/STM-1/OC-3 ATM TRANSCEIVER |
| S3032 | SONET/SDH/ATM OC-3/12 Transceiver W/CDR(頻率可選的SONET/SDH收發(fā)器（完全集成OC-3/12接口器件）) |
| S3033 | SONET/SDH/ATM OC-3/12 Transceiver(帶片上高頻鎖相環(huán)的SONET/SDH收發(fā)器（完全集成OC-3/12接口器件）) |
| S3035 | SONET/SDH/ATM OC-3/12 Transceiver W/CDR(頻率可選，帶片上高頻鎖相環(huán)的SONET/SDH收發(fā)器（完全集成OC-3/12接口器件）) |
| S3037 | SONET/SDH/ATM OC-3/12 Transceiver W/CDR(19.44和77.76 MHz兩種頻率可選的SONET/SDH收發(fā)器) |
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| S3031B | 制造商:AppliedMicro 功能描述: |
| S3031BH0 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:E4/STM-1/OC-3 ATM TRANSCEIVER |
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