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參數(shù)資料
| 型號(hào)： | S3014 |
| 廠(chǎng)商： | Applied Micro Circuits Corp. |
| 英文描述： | SONET/SDH Clock Recovery and Synthesis Unit(SONET/SDH時(shí)鐘恢復(fù)和合成器件) |
| 中文描述： | SONET / SDH的時(shí)鐘恢復(fù)和合成單元（SONET / SDH的時(shí)鐘恢復(fù)和合成器件） |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大?。?/td> | 99K |
| 代理商： | S3014 |
6
S3014
SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT
Performance Specifications
Parameter
Min
Typ
Max
Units
Condition
Nominal VCO
Center Frequency
622.08
MHz
Given REFCLK = SERCLK
÷
4,
12 or SERCLK
÷
32 per SEL
<2:0> settings
In CSU mode, given :
Clock Synthesis Output
Jitter
OC-3/STS-3
OC-12/STS-12
.005
.015
.01
64
.03
48
UI(rms)
ps (rms)
UI(rms)
ps (rms)
56ps rms jitter on REFCLK
in 12 KHz to 1 MHz band
14.1 ps rms jitter on REFCLK
in 12 KHz to 1 MHz band
Clock Recovery Output
Jitter
Reference Clock
Frequency Tolerance
Clock Synthesis
Clock Recovery
OC-3/STS-3
OC-12/STS-12
Capture Range
.01
UI(rms)
rms jitter, in lock
-20
-100
20
100
ppm
ppm
Required to meet SONET output
frequency specification
Lock Range
Clock Output
Duty Cycle
Acquisition Lock Time
OC-3/STS-3
OC-12/STS-12
45
±
200
+8,-12
55
ppm
%
%
With respect to fixed reference
frequency
Minimum transition density of
20%
64
16
μ
sec
With device already powered up
and valid REFCLK.
Reference Clock
Input Duty Cycle
30
70
% of
period
Reference Clock Rise &
Fall Times
2.0
ns
10% to 90% of amplitude
ECL Output Rise & Fall
Times
850
ps
10% to 90%, 50
to -2V
equivalent load, 5 pf cap
1. These specs can be achieved with either a 51.84 MHz or a 155.52 MHz Reference Clock.
2. Noise on REFCLK should be less than 14.1 ps rms in a jitter frequency band from 12 KHz to 1 MHz.
3. Specifications based on design values. Not tested.
3
2,3
1
SEL2
SEL1 SEL0
0
0
1
1
0
0
SERCLKO
622.08 MHz
622.08 MHz
622.08 MHz
622.08 MHz
155.52 MHz
155.52 MHz
REFCKOUT
51.84 MHz
19.44 MHz
19.44 MHz
—
51.84 MHz
19.44 MHz
REFCKIN
51.84 MHz
19.44 MHz
19.44 MHz
155.52 MHz
51.84 MHz
19.44 MHz
0
0
0
0
1
1
0
1
0
1
0
1
Table 1. Mode Select
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