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參數(shù)資料
| 型號(hào)： | S29NS256P0PBJW003 |
| 廠商： | SPANSION LLC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | MirrorBit Flash Family |
| 中文描述： | 16M X 16 FLASH 1.8V PROM, 80 ns, PBGA64 |
| 封裝： | 6.20 X 7.70 MM , LEAD FREE, TFBGA-64 |
| 文件頁(yè)數(shù)： | 85/86頁(yè) |
| 文件大?。?/td> | 2234K |
| 代理商： | S29NS256P0PBJW003 |
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February 20, 2007 S29NS-P_00_A1
S29NS-P MirrorBit
TM
Flash Family
85
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
12. Revision History
Section
Description
Revision A (June 29, 2006)
Initial release
Revision A1 (February 20, 2007)
Global
The tAVDS specification is changed from 4 ns to 5 ns
The wait state for 83 MHz is changed to 8
ICC3(Max) is changed to 70 μA and ICC6(Max) is changed to 40 μA
VIL (Min) is changed to -0.2 V
tOE (Max) in both Asynchronous & Synchronous modes is changed to 9 ns across all frequencies
tCEZ (Max) is changed to 10 ns across all frequencies
tOEZ (Max) in both Asynchronous & Synchronous modes is changed to 10 ns across all frequencies
tACH(Min) is changed to 6 ns (66 MHz) and 5 ns (83 MHz and 108 MHz)
tRDY(Max) is changed to 10 ns
tRACC(Max) is changed to 7.6 ns for 108 MHz
tOEH(Min) in Asynchronous mode is changed to 10 ns for 108 MHz
Erase and Programing Performance table is updated
tCE in Asynchronous mode is changed to 83ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S29NS256P0SBJW000 | MirrorBit Flash Family |
| S29NS256P0SBJW003 | MirrorBit Flash Family |
| S29NS256PABBJW000 | MirrorBit Flash Family |
| S29NS256PABBJW003 | MirrorBit Flash Family |
| S29NS512P | MirrorBit Flash Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29NS256P0SBJW000 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:MirrorBit Flash Family |
| S29NS256P0SBJW003 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:MirrorBit Flash Family |
| S29NS256PABBJW000 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:MirrorBit Flash Family |
| S29NS256PABBJW003 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:MirrorBit Flash Family |
| S29NS512P | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:MirrorBit Flash Family |
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