參數(shù)資料
型號: S29NS256N0SBJW002
廠商: SPANSION LLC
元件分類: DRAM
英文描述: Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
中文描述: 16M X 16 FLASH 1.8V PROM, 80 ns, PBGA48
封裝: 10 X 11 MM, LEAD FREE, FBGA-48
文件頁數(shù): 58/86頁
文件大?。?/td> 1036K
代理商: S29NS256N0SBJW002
56
S29NS-N MirrorBit Flash Family
S29NS-N_00_A12 June 13, 2006
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously
with DQ6–DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing
status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid
data, the data outputs on DQ6–DQ0 may be still invalid. Valid data on DQ7–DQ0 will appear on successive
read cycles.
Table 12.2 on page 60
shows the outputs for Data# Polling on DQ7.
Figure 12.1 on page 56
shows the Data#
Polling algorithm.
Figure 19.9 on page 72
in the
AC Characteristics
section shows the Data# Polling timing
diagram.
Figure 12.1
Data# Polling Algorithm
Notes
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being
erased. During chip erase, a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
DQ7 = Data
Yes
No
No
DQ5 = 1
No
Yes
Yes
FAIL
PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data
START
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