參數(shù)資料
型號： S29NS256N0SBJW002
廠商： SPANSION LLC
元件分類： DRAM
英文描述： Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
中文描述： 16M X 16 FLASH 1.8V PROM, 80 ns, PBGA48
封裝： 10 X 11 MM, LEAD FREE, FBGA-48
文件頁數(shù)： 40/86頁
文件大小： 1036K
代理商： S29NS256N0SBJW002
38
S29NS-N MirrorBit Flash Family
S29NS-N_00_A12 June 13, 2006
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
10.3.3
Programmable Wait State
The host system should set
CR13-CR11
to 101/100/011 for a clock frequency of 80/66 MHz for the system/
device to execute at maximum speed.
Table 10.2
describes the typical number of clock cycles (wait states) for various conditions.
10.3.4
Handshaking
For optimal burst mode performance, the host system must set the appropriate number of wait states in the
flash device depending on the clock frequency.
The autoselect function allows the host system to determine whether the flash device is enabled for
handshaking.
10.3.5
Burst Length Configuration
The device supports four different read modes: continuous mode, and 8, 16, and 32 word linear with or
without wrap around modes. A continuous sequence (default) begins at the starting address and advances
the address pointer until the burst operation is complete. If the highest address in the device is reached
during the continuous burst read mode, the address pointer wraps around to the lowest address.
For example, an eight-word linear read with wrap around begins on the starting address written to the device
and then advances to the next 8 word boundary. The address pointer then returns to the 1st word after the
previous eight word boundary, wrapping through the starting location. The sixteen- and thirty-two linear wrap
around modes operate in a fashion similar to the eight-word mode.
Table 10.3
shows the
CR2-CR0
and settings for the four read modes.
Notes
1. Upon power-up or hardware reset the default setting is continuous.
2. All other conditions are reserved.
10.3.6
Burst Wrap Around
By default, the device will perform burst wrap around with
CR3
set to a ‘1’. Changing the
CR3
to a ‘0’ disables
burst wrap around.
10.3.7
RDY Configuration
By default, the device is set so that the RDY pin will output V
OH
whenever there is valid data on the outputs.
The device can be set so that RDY goes active one data cycle before active data.
CR8
determines this
setting; “1” for RDY active (default) with data, “0” for RDY active one clock cycle before valid data.
Table 10.2
Wait States for Handshaking
Conditions at Address
Typical No. of Clock Cycles after AVD# Low
80 MHz
66 MHz
Initial address (V
CCQ
= 1.8 V)
7
6
Table 10.3
Burst Length Configuration
Burst Modes
Address Bits
CR2
CR1
CR0
Continuous
0
0
0
8-word linear
0
1
0
16-word linear
0
1
1
32-word linear
1
0
0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29NS256N0SBJW003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS256P 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family
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S29NS256P0PBJW003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family
S29NS256P0SBJW000 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family
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