參數(shù)資料
型號: S29NS032J0PBFW000
廠商: SPANSION LLC
元件分類: DRAM
英文描述: 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
中文描述: 2M X 16 FLASH 1.8V PROM, 65 ns, PBGA44
封裝: 7.70 X 6.20 MM, LEAD FREE, FBGA-44
文件頁數(shù): 70/85頁
文件大小: 799K
代理商: S29NS032J0PBFW000
66
S29NS-J
S29NS-J_00_A10 March 22, 2006
D a t a S h e e t
AC Characteristics
Note:
Devices should be programmed with wait states as discussed in the “Programmable Wait State” section on page 16.
Figure 22. Initial Access at 3Eh with Address Boundary Latency
Note:
If t
AVDSM
> 1 CLK cycle, wait state usage is reduced. Figure shows 40 MHz clock, handshaking enabled. Wait state usage is
4 clock cycles instead of 5. Note that t
AVDSM
must be less than 76 μs for burst operation to begin
.
Figure 23. Example of Extended Valid Address Reducing Wait State Usage
CLK
AVD#
RDY
Address
High-Z
A/DQ15
A/DQ0
OE#
D0
D1
D2
device is programmable from 2 to 7 total cycles
during initial access (here, programmable wait state
function is set to 04h; 6 cycles total)
2 additional
wait states if
address is
at boundary
AVD# low with clock
present enables
burst read mode
Address
Amax
A16
t
OE
CLK
AVD#
RDY
Hi-Z
A/DQ
OE#
CE#
D0
D1
D2
t
IACC
t
AVDSM
Addresses
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