參數(shù)資料
型號(hào)： S29GL128N10FFIV13
廠商： SPANSION LLC
元件分類(lèi)： DRAM
英文描述： 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit⑩ Process Technology
中文描述： 8M X 16 FLASH 3V PROM, 100 ns, PBGA64
封裝： 13 X 11 MM, 1MM PITCH, LEAD FREE, FBGA-64
文件頁(yè)數(shù)： 54/100頁(yè)
文件大?。?/td> 952K
代理商： S29GL128N10FFIV13
52
S29GL-N MirrorBit Flash Family
S29GL-N_00_B3 October 13, 2006
D a t a S h e e t
tal bit programming) is permitted. Word programming is supported for backward
compatibility with existing Flash driver software and for occasional writing of individual words.
Use of Write Buffer Programming is strongly recommended for general programming use
when more than a few words are to be programmed. The effective word programming time
using Write Buffer Programming is much shorter than the single word programming time.
Any bit cannot be programmed from
0
back to a
1
.
Attempting to do so may cause the
device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was
successful. However, a succeeding read shows that the data is still
0
. Only erase operations
can convert a
0
to a
1
.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device faster than using
the standard program command sequence. The unlock bypass command sequence is initiated
by first writing two unlock cycles. This is followed by a third write cycle containing the unlock
bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock
bypass program command sequence is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass program command, A0h; the second cycle
contains the program address and data. Additional data is programmed in the same manner.
This mode dispenses with the initial two unlock cycles required in the standard program com-
mand sequence, resulting in faster total programming time.
Table 12 on page 63
and
Table 14
on page 65
show the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset
commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle
unlock bypass reset command sequence. (See
Table 12 on page 63
and
Table 14 on
page 65
).
W rite Buffer Programming
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one
programming operation. This results in faster effective programming time than the standard
programming algorithms. The Write Buffer Programming command sequence is initiated by
first writing two unlock cycles. This is followed by a third write cycle containing the Write
Buffer Load command written at the Sector Address in which programming occurs. The fourth
cycle writes the sector address and the number of word locations, minus one, to be pro-
grammed. For example, if the system programs six unique address locations, then 05h should
be written to the device. This tells the device how many write buffer addresses are loaded
with data and therefore when to expect the Program Buffer to Flash command. The number
of locations to program cannot exceed the size of the write buffer or the operation aborts.
The fifth cycle writes the first address location and data to be programmed. The
write-buffer-page is selected by address bits A
MAX
–A
4
. All subsequent address/data pairs
must fall within the selected-write-buffer-page. The system then writes the remaining ad-
dress/data pairs into the write buffer. Write buffer locations may be loaded in any order.
The write-buffer-page address must be the same for all address/data pairs loaded into the
write buffer. (This means Write Buffer Programming cannot be performed across multiple
write-buffer pages. This also means that Write Buffer Programming cannot be performed
across multiple sectors. If the system attempts to load programming data outside of the se-
lected write-buffer page, the operation aborts.)
Note that if a Write Buffer address location is loaded multiple times, the address/data pair
counter is decremented for every data load operation. The host system must therefore ac-
count for loading a write-buffer location more than once. The counter decrements for each
data load operation, not for each unique write-buffer-address location. Note also that if an
address location is loaded more than once into the buffer, the final data loaded for that ad-
dress is programmed.
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