- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365393 > S29GL128N10FFIV13 (SPANSION LLC) 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit⑩ Process Technology PDF資料下載
參數(shù)資料
| 型號： | S29GL128N10FFIV13 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit⑩ Process Technology |
| 中文描述： | 8M X 16 FLASH 3V PROM, 100 ns, PBGA64 |
| 封裝： | 13 X 11 MM, 1MM PITCH, LEAD FREE, FBGA-64 |
| 文件頁數(shù)： | 4/100頁 |
| 文件大小： | 952K |
| 代理商： | S29GL128N10FFIV13 |
第1頁第2頁第3頁當前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁
2
S29GL-N MirrorBit Flash Family
S29GL-N_00_B3 October 13, 2006
D a t a S h e e t
General Description
The S29GL512/256/128N family of devices are 3.0V single power flash memory manufac-
tured using 110 nm
MirrorBit technology. The S29GL512N is a 512 Mbit, organized as
33,554,432 words or 67,108,864 bytes. The S29GL256N is a 256 Mbit, organized as
16,777,216 words or 33,554,432 bytes. The S29GL128N is a 128 Mbit, organized as
8,388,608 words or 16,777,216 bytes. The devices have a 16-bit wide data bus that can also
function as an 8-bit wide data bus by using the BYTE# input. The device can be programmed
either in the host system or in standard EPROM programmers.
Access times as fast as 90 ns (S29GL128N, S29GL256N), 100 ns (S29GL512N) are available.
Note that each access time has a specific operating voltage range (V
CC
) and an I/O voltage
range (V
IO
), as specified in the
Product Selector Guide on page 6
and the
Ordering Infor-
mation on page 12
. The devices are offered in a 56-pin TSOP or 64-ball Fortified BGA
package. Each device has separate chip enable (CE#), write enable (WE#) and output enable
(OE#) controls.
Each device requires only a
single 3.0 volt pow er supply
for both read and write functions.
In addition to a V
CC
input, a high-voltage
accelerated program (
WP#/
ACC)
input provides
shorter programming times through increased current. This feature is intended to facilitate
factory throughput during system production, but may also be used in the field if desired.
The devices are entirely command set compatible with the
J EDEC single-pow er-supply
Flash standard
. Commands are written to the device using standard microprocessor write
timing. Write cycles also internally latch addresses and data needed for the programming and
erase operations.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed
without affecting the data contents of other sectors. The device is fully erased when shipped
from the factory.
Device programming and erasure are initiated through command sequences. Once a program
or erase operation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6
(toggle)
status bits
or monitor the
Ready/ Busy# ( RY / BY # )
output to determine whether
the operation is complete. To facilitate programming, an
Unlock Bypass
mode reduces com-
mand sequence overhead by requiring only two write cycles to program data instead of four.
The
Enhanced
VersatileI / O
(V
IO
) control allows the host system to set the voltage levels
that the device generates and tolerates on all input levels (address, chip control, and DQ input
levels) to the same voltage level that is asserted on the V
IO
pin. This allows the device to
operate in a 1.8 V or 3 V system environment as required.
Hardw are data protection
measures include a low V
CC
detector that automatically inhibits
write operations during power transitions.
Persistent Sector Protection
provides in-sys-
tem, command-enabled protection of any combination of sectors using a single power supply
at V
CC
.
Passw ord Sector Protection
prevents unauthorized write and erase operations in
any combination of sectors through a user-defined 64-bit password.
The
Erase Suspend/ Erase Resume
feature allows the host system to pause an erase op-
eration in a given sector to read or program any other sector and then complete the erase
operation. The
Program Suspend/ Program Resume
feature enables the host system to
pause a program operation in a given sector to read any other sector and then complete the
program operation.
The
hardw are RESET# pin
terminates any operation in progress and resets the device,
after which it is then ready for a new operation. The RESET# pin may be tied to the system
reset circuitry. A system reset would thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
相關PDF資料 |
PDF描述 |
|---|---|
| S29GL128N10FFIV20 | 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit⑩ Process Technology |
| S29GL128N10FFIV22 | 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit⑩ Process Technology |
| S29GL128N10FFIV23 | 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit⑩ Process Technology |
| S29GL128N10TAI010 | 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit⑩ Process Technology |
| S29GL128N10TAI012 | 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit⑩ Process Technology |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| S29GL128N10TF101 | 制造商:Spansion 功能描述: |
| S29GL128N10TFI010 | 功能描述:IC FLASH 制造商:cypress semiconductor corp 系列:GL-N 包裝:托盤 零件狀態(tài):在售 存儲器類型:非易失 存儲器格式:閃存 技術:FLASH - NOR 存儲容量:128Mb （16M x 8，8M x 16） 寫周期時間 - 字，頁:100ns 訪問時間:100ns 存儲器接口:并聯(lián) 電壓 - 電源:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C（TA） 安裝類型:表面貼裝 封裝/外殼:56-TFSOP（0.724"，18.40mm 寬） 供應商器件封裝:56-TSOP 標準包裝:91 |
| S29GL128N10TFI020 | 制造商:Spansion 功能描述:S29GL128N10TFI020 制造商:Spansion 功能描述:Flash - NOR IC |
| S29GL128N11FAI020 | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 128M-Bit 16M x 8/8M x 16 110ns 64-Pin Fortified BGA Tray |
| S29GL128N11FAI023 | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 128M-Bit 16M x 8/8M x 16 110ns 64-Pin Fortified BGA T/R |
發(fā)布緊急采購，3分鐘左右您將得到回復。