參數(shù)資料
型號: S29CD016J1MQFM102
廠商: Spansion Inc.
英文描述: 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
中文描述: 32/16兆位的CMOS 2.6伏或3.3伏,只有同時讀/寫,雙啟動,突發(fā)模式閃存記憶體與VersatileI /輸出
文件頁數(shù): 25/76頁
文件大?。?/td> 1245K
代理商: S29CD016J1MQFM102
September27,2006 S29CD-J_CL-J_00_B1
S29CD-J & S29CL-J Flash Family
23
D a t a
S h e e t
( P r e l i m i n a r y )
Figure 8.3
End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Burst Operation
Note
Operation is shown for the 32-bit data bus. Figure shown with 3-CLK initial access delay configuration, linear address, 4-doubleword burst,
output on rising CLD edge, data hold for 1-CLK, IND/WAIT# asserted on the last transfer before wrap-around.
8.4.2
Initial Burst Access Delay
Initial Burst Access Delay is defined as the number of clock cycles that must elapse from the first valid clock
edge after ADV# assertion (or the rising edge of ADV#) until the first valid CLK edge when the data is valid.
Burst access is initiated and the address is latched on the first rising CLK edge when ADV# is active or upon
a rising ADV# edge, whichever comes first. The Initial Burst Access Delay is determined in the Configuration
Register (CR13-CR10). Refer to
Table 8.5
for the initial access delay configurations under CR13-CR10. See
Figure 8.4
for the Initial Burst Delay Control timing diagram.
Note that the Initial Access Delay for a burst
access has no effect on asynchronous read operations.
Table 8.3
Valid Configuration Register Bit Definition for IND/WAIT#
CR9
(DOC)
CR8
(WC)
CR6
(CC)
Definition
0
0
1
IND/WAIT# = V
IL
for 1-CLK cycle, Active on last transfer, Driven on rising CLK edge
IND/WAIT# = V
IL
for 1-CLK cycle, Active on second to last transfer, Driven on rising
CLK edge
0
1
1
CE#
CLK
ADV#
Addre
ss
e
s
OE#
D
a
t
a
Addre
ss
1
Addre
ss
2
Inv
a
lid
D1
D2
D
3
D0
Addre
ss
1 L
a
tched
3
Clock Del
a
y
IND/WAIT#
V
IL
V
IH
Table 8.4
Burst Initial Access Delay
CR13
CR12
CR11
CR10
Initial Burst Access (CLK cycles)
0
0
0
1
3
0
0
1
0
4
0
0
1
1
5
0
1
0
0
6
0
1
0
1
7
0
1
1
0
8
0
1
1
1
9
相關(guān)PDF資料
PDF描述
S29CD016J1MQFM103 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
S29CD016J1MQFM133 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
S29GL064M90FCIR83 256,128,64,32,Megabit 3.0 Volt-only Page Mode Flash Memory featuring 0.23 レm MirrorBit Process Technology
S29GL064M90TAIR32 256,128,64,32,Megabit 3.0 Volt-only Page Mode Flash Memory featuring 0.23 レm MirrorBit Process Technology
S29GL064M90TAIR33 256,128,64,32,Megabit 3.0 Volt-only Page Mode Flash Memory featuring 0.23 レm MirrorBit Process Technology
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29CD016J1MQFM103 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
S29CD016J1MQFM133 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
S29CD032G 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 2.5 VOLT ONLY BURST MODE DUAL BOOT, SIMULTANEOUS READ /WRITE FLASH MEMORY
S29CD032G0JFAA000 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
S29CD032G0JFAA002 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O