參數(shù)資料
型號(hào)： S29CD016J1MQFM102
廠(chǎng)商： Spansion Inc.
英文描述： 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
中文描述： 32/16兆位的CMOS 2.6伏或3.3伏，只有同時(shí)讀/寫(xiě)，雙啟動(dòng)，突發(fā)模式閃存記憶體與VersatileI /輸出
文件頁(yè)數(shù)： 23/76頁(yè)
文件大小： 1245K
代理商： S29CD016J1MQFM102
September27,2006 S29CD-J_CL-J_00_B1
S29CD-J & S29CL-J Flash Family
21
D a t a
S h e e t
( P r e l i m i n a r y )
banks was in the middle of either a program or erase operation when RESET# was asserted, the user must
wait a period of t
READY
before accessing that bank.
Asserting RESET# during a program or erase operation leaves erroneous data stored in the address
locations being operated on at the time of device reset. These locations need updating after the reset
operation is complete. See Section 18.4 for timing specifications.
Asserting RESET# active during V
CC
and V
IO
power-up is required to guarantee proper device initialization
until V
CC
and V
IO
have reached their steady state voltages. See Section 18.1.
8.4
Synchronous (Burst) Read Mode & Configuration Register
When a series of adjacent addresses need to be read from the device, the synchronous (or burst read) mode
can be used to significantly reduce the overall time needed for the device to output array data. After an initial
access time required for the data from the first address location, subsequent data is output synchronized to a
clock input provided by the system.
The device offers a linear method of burst read operation which is discussed in
Section 8.4.1,
2-, 4-, 8-
Double Word Linear Burst Operation
on page 22
.
Since the device defaults to asynchronous read mode after power-up or a hardware reset, the configuration
register must be set in order to enable the burst read mode. Other Configuration Register settings include the
number of wait states to insert before the initial word (t
IACC
) of each burst access and when RDY indicates
that data is ready to be read. Prior to entering the burst mode, the system first determines the configuration
register settings (and read the current register settings if desired via the Read Configuration Register
command sequence), then write the configuration register command sequence. See
Section 8.4.3,
Configuration Register
on page 24
, and
Table 20.1,
Memory Array Command Definitions (x32 Mode)
on page 69
for further details. Once the configuration register is written to enable burst mode operation, all
subsequent reads from the array are returned using the burst mode protocols.
Figure 8.2
Synchronous/Asynchronous State Diagram
The device outputs the initial word subject to the following operational conditions:
t
IACC
specification: The time from the rising edge of the first clock cycle after addresses are latched to valid
data on the device outputs.
Configuration register setting CR13-CR10: The total number of clock cycles (wait states) that occur before
valid data appears on the device outputs. The effect is that t
IACC
is lengthened.
Power-
u
p/
H
a
rdw
a
re Re
s
et
A
s
ynchrono
us
Re
a
d
Mode Only
S
ynchrono
us
Re
a
d
Mode Only
S
et B
u
r
s
t Mode
Config
u
r
a
tion Regi
s
ter
Comm
a
nd for
S
ynchrono
us
Mode
(D15 = 0)
S
et B
u
r
s
t Mode
Config
u
r
a
tion Regi
s
ter
Comm
a
nd for
A
s
ynchrono
us
Mode
(D15 = 1)
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S29CD016J1MQFM133 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
S29CD032G 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:CMOS 2.5 VOLT ONLY BURST MODE DUAL BOOT, SIMULTANEOUS READ /WRITE FLASH MEMORY
S29CD032G0JFAA000 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
S29CD032G0JFAA002 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
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