參數(shù)資料
型號： S2104
廠商： Applied Micro Circuits Corp.
英文描述： Quad Fibre Channel Device(帶鎖相環(huán)時鐘合成器的光纖通道四收發(fā)器)
中文描述： 四光纖通道設(shè)備（帶鎖相環(huán)時鐘合成器的光纖通道四收發(fā)器）
文件頁數(shù)： 10/33頁
文件大?。?/td> 342K
代理商： S2104
10
QUAD FIBRE CHANNEL DEVICE
S2104
October 6, 2000 / Revision E
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Table 5. Output Clock Mode (TMODE = 1)
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Table 5A. S2104 Data Clocking
Data Output
Data is output on the DOUT[0:9] outputs. The
COM_DET signal is used to indicate the reception of a
valid K28.5 character.
The S2104 TTL outputs are optimized to drive 65
line impedances. Internal source matching provides
good performance on unterminated lines of reason-
able length.
Parallel Output Clock Rate
Two output clock modes are supported, as shown in
Table 5. When CMODE is High, a complementary
TTL clock at the data rate is provided on the RBC1/
0x outputs. Data should be clocked on the rising
edge of RBC1x. When CMODE is Low, a comple-
mentary TTL clock at 1/2 the data rate is provided.
Data should be latched on the rising edge of RBC1x
and the rising edge of RBC0x.
In Fibre Channel applications, multiple consecutive
K28.5 characters cannot be generated. However, for
serial backplane applications this can occur. The
S2104 must be able to operate properly when mul-
tiple K28.5 characters are received. After the first
K28.5 is detected and aligned, the RBC1/0x clock
will operate without glitches or loss of cycles.
Receiver Output Clocking
The S2104 parallel output clock source is deter-
mined by the TMODE selection. When REFCLK
clocking is selected (TMODE = Low), the parallel
output clocks (RCxP/N) are sourced from the TCLKA
input. When TCLK clocking is selected (External
Clocking Mode), the parallel output clocks are de-
rived from the recovered clock from each channel.
Table 5A describes the receiver output clocking op-
tions available.
When TCLKA is the output clock source, REFCLK
and TCLKA must equal the parallel word rate
(CLKSEL = Low). Additionally, the recovered clocks
and the clock input on TCLKA must be frequency
locked in order to avoid overflow/underflow of the
internal FIFOs. The propagation delay between
TCLKA and DOUTx, listed in Table 21, shows that
the phase delay between TCLKA and the RCxP/N
outputs may vary more than a bit time based on
process variation.
The recommended clocking configuration for exter-
nal clocking mode (REFCLK input clocking) is shown
in Figure 8. TCLKA is sourced from TCLKO, which is
frequency locked to the Reference clock input.
REFCLK
SerDes
TCLKA
REF
OSCILLATOR
Controller/MAC
ASIC/FPGA
TCLKO
PLL
Parallel Data
RCxP/N
2
Recovered
Clock
Figure 8. External Receiver Clocking
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