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參數(shù)資料
| 型號(hào)： | S2091 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | 2.5 Gbit Port Bypass Circuit for Fibre Channel Arbitrated Loop(用于光纖通道仲裁環(huán)路的端口旁路電路) |
| 中文描述： | 2.5千兆位端口旁路電路的光纖通道仲裁環(huán)路（用于光纖通道仲裁環(huán)路的端口旁路電路） |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 108K |
| 代理商： | S2091 |
8
2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP
S2091
Input Structures
Two input structures exist in this part; TTL and high speed, differential inputs. The LVTTL inputs will interface
with any LVTTL outputs. The high speed, differential inputs can be AC coupled per the FC-PH specification.
Therefore, the high speed, differential input buffers are biased at Vcc -0.65V. Refer to Figure 7 for high speed
differential input termination.
Figure 8. Output
Backplane
S2091
GND
VCC
50
50
Figure 7. Input Termination
S2091
100
Biased at Vcc -0.65V
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