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參數(shù)資料
| 型號(hào)： | S1T8528X01-Q0R0 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | IC, 10/100 BASE-T PHY TRANSCEIVER |
| 中文描述： | 強(qiáng)化- 1射頻集成電路芯片CT0 |
| 文件頁數(shù)： | 6/35頁 |
| 文件大?。?/td> | 1905K |
| 代理商： | S1T8528X01-Q0R0 |
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S1T8528
ENHANCED-1 CHIP CT0 RF IC
6
34
2MI
Input terminal of mixer 2. Output from mixer 1 is entered to mixer 2 input terminal via
10.7MHz ceramic filter. Second mixer converts frequency to second intermediate
frequency ( 455kHz: AM IF ).
35
2MO
Output terminal of Mixer 2. Second intermediate frequency ( 455kHz ), generated by
mixing first intermediate frequency ( 10.7MHz ) and Second Local Oscillator is output.
36
37
2LOI
2LOI
Input terminal of second local oscillator. These pins generate 2
’
nd local oscillation
frequency and are designed as colpitt type oscillator.
10.24MHz or 10.245MHz can be applied as for 2
’
nd local oscillator.
38
1MO
Output terminal of mixer 1.
The signal from mixer 1 and the frequency of the first local oscillator are mixed to
produce the first intermediate frequency, which is the output through this terminal. The
output terminal is an emitter follower with an output impedance of 330
to match the
330
input / output impedance of the 10.7MHz ceramic filter.
39
40
1LOI
1LOI
Input terminal of the first local oscillator.
The local oscillator is a voltage controlled oscillator. Local oscillation frequency and
received frequency are mixed at mixer 1 and then converted to the first intermediate
frequency of 10.7MHz or 10.695MHz.
41
VCO
RX
The terminal which variable capacitor is included in the chip. Used as an input terminal
where 1st local oscillation frequency is changed by varying the capacitor connected
between 1st local oscillator terminals.
The internal variable capacitor has the value of 18.73 ~ 15.86 pF depending on the
applied voltage. ( 1.0 ~ 2.0V )
42
43
1MI
1MI
Input terminal of Mixer1. This mixer is made of doubly balanced multiplier.
The received signal amplified at RF AMP is input to this terminal.
44
GND
(PLL)
Ground.
Ground for analog at PLL.
45
PDR
Phase detector output terminal of the receiver at PLL.
If f
RX
> f
REF
or f
RX
is Leading
→
The output is negative pulse
If f
RX
< f
REF
or f
RX
is Lagging
→
The output is positive pulse
If f
RX
= f
REF
and the same phase
→
The output is high impedance
46
V
REF(RF)
An internal PMOS pass transistor provides power supplier for the RF pre amplifier.
PMOS pass transistor is on in Active/Rx mode and off in Standby/Inactive mode.
47
V
REF(PLL)
PLL voltage reference output pin.
An internal voltage regulator provides a stable power supply voltage for the RX and TX
PLLs. (2.05V)
48
TIF
Input terminal of TX channel counter.
AC coupling with TX VCO.
Minimum input level is 300 mVp-p ( at 60MHz ).
PIN DESCRIPTION (Continued)
Pin No
Symbol
Description
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