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參數(shù)資料
| 型號： | S1R72V27B05 |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA60 |
| 封裝： | 5 X 5 MM, 0.50 MM PITCH, PLASTIC, TFBGA-60 |
| 文件頁數(shù)： | 6/42頁 |
| 文件大?。?/td> | 426K |
| 代理商： | S1R72V27B05 |
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4. Explanation of Functions
S1R72V27 Data Sheet (Rev. 1.00)
EPSON
9
USB FIFO
Endpoint
USB Host
PING token
Free quantity >=
MaxPktSize
ACK handshake
OUT token
CPU
FIFO_Empty
PING token
Free quantity <
MaxPktSize
Read
Write
PING transaction
(ACK response)
OUT transaction
(Data receipt)
PING transaction
(NAK response)
Transfer received
NAK handshake
FIFO_Full
FIFO_Empty
PING token
Free quantity >=
MaxPktSize
PING transaction
(ACK response)
Empty
Data
DATA packet
NYET handshake
Read
ACK handshake
Note: PING transactions are performed only in High Speed mode.
Figure 4-5 Typical data flow (with FIFO assigned for MaxPktSize and OUT transfer)
4.6.4
USB Device Port External Circuits
The LSI USB Port 0 has internal FS and HS device termination resistors, eliminating the
need for the components normally used to adjust impedance. This allows a DP/DM line to
be connected directly between the LSI terminal and the connector. Note that the
appropriate components must be used to ensure static electricity protection and to
implement EMI precautions.
The VBUS terminal uses a 5 V input and does not require external voltage conversion. A
protection circuit is recommended, since certain commercially-available USB host and hub
products may apply surge voltages exceeding VBUS ratings.
Refer to the separately provided PCB Design Guidelines for S1R72V Series USB 2.0
Hi-Speed.
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