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參數(shù)資料
| 型號： | S1R72V27B05 |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA60 |
| 封裝： | 5 X 5 MM, 0.50 MM PITCH, PLASTIC, TFBGA-60 |
| 文件頁數(shù)： | 2/42頁 |
| 文件大?。?/td> | 426K |
| 代理商： | S1R72V27B05 |
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4. Explanation of Functions
S1R72V27 Data Sheet (Rev. 1.00)
EPSON
5
4.2
Reset
This LSI includes a hard reset function using the external XRESET terminal and a soft reset function
using register settings.
4.2.1
Hard Reset
Start up from reset status when power is turned on, then cancel the reset after confirming
power on.
4.2.2
Soft Reset
Circuits related to the USB port or individual internal USB analog macros can be reset via
software. This LSI can be soft reset using the ChipReset.AllReset bit. The
ChipReset.ResetMTM bit is used to reset USB analog macros. Note, however, that analog
macros should only be reset in the sleep state.
4.3
Clock
This LSI contains an internal oscillator and feedback resistor (1 M
) and supports clock generation
using an external oscillator. External clock input is supported via the CLKIN terminal.
The oscillator frequency supports 12 MHz or 24 MHz using the internal oscillator. Frequencies of 12,
24, or 48 MHz are supported via the external input.
Figure 4-2 shows a typical connection arrangement for an oscillation circuit. Contact the oscillator
manufacturer to determine circuit constants, as Cd, Cg, and Rd in the oscillator circuit must be
matched, based on the oscillator.
XI
XO
Cd
Rd
Cg
Figure 4-2 Clock generation using the internal oscillator and external oscillator
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