參數(shù)資料
型號(hào): S1R72V27B05
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA60
封裝: 5 X 5 MM, 0.50 MM PITCH, PLASTIC, TFBGA-60
文件頁(yè)數(shù): 3/42頁(yè)
文件大?。?/td> 426K
代理商: S1R72V27B05
4. Explanation of Functions
6
EPSON
S1R72V27 Data Sheet (Rev. 1.00)
4.4
Power Management
This LSI includes a power management function featuring two power management states, SLEEP
and ACTIVE, together with the CPU_Cut power management state. (See Figure 4-3.)
All function blocks are active in the ACTIVE state, whereas only the bare minimum circuits
necessary for restarting from standby mode are active in SLEEP state. CPU_Cut mode minimizes
power consumption attributable to the CPU-I/F input buffer.
ACTIVE
CPU
-I/F
FIFO
SIE
UTM
OSC
SLEEP
CPU
-I/F*
FIFO
SIE
UTM
OSC
CPU_Cut
CPU
-I/F**
FIFO
SIE
UTM
OSC
Active
Inactive
* The CPU-I/F is only partially active in SLEEP state.
The asynchronous access register can be accessed.
** CPU-I/F operation is suspended in CPU_Cut to minimize
power consumption attributable to the I/O input buffer.
Figure 4-3 Power management states
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