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參數(shù)資料
| 型號(hào)： | S1R72V18B10 |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA121 |
| 封裝： | PLASTIC, FBGA-121 |
| 文件頁數(shù)： | 9/37頁 |
| 文件大小： | 365K |
| 代理商： | S1R72V18B10 |
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4. Explanation of Functions
12
EPSON
S1R72V18 Data Sheet (Rev. 1.00)
4.7.4
USB Host Port External Circuits
The LSI ports have internal USB host termination resistors, including an HS termination
resistor, eliminating the need for the external components normally used to adjust
impedance. This allows a DP/DM line to be connected between the LSI terminal and the
connector. Note that the appropriate components must be used to ensure static electricity
protection and to implement EMI precautions.
An external VBUS control component is required for the VBUS.
4.8
FIFO
Each port on the LSI includes 4.5 kB of USB FIFO for use with USB data transfers. The USB FIFO
capacity for each endpoint or channel can be assigned as desired using the register settings.
Transfers are possible between the USB-I/F and CPU-I/F via the USB FIFO.
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