參數(shù)資料
型號(hào)： S1R72V18B10
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA121
封裝： PLASTIC, FBGA-121
文件頁(yè)數(shù)： 7/37頁(yè)
文件大?。?/td> 365K
代理商： S1R72V18B10
4. Explanation of Functions
10
EPSON
S1R72V18 Data Sheet (Rev. 1.00)
4.7
USB Host I/F
The LSI USB Port 0 and Port 1 support high-speed specification USB host functions complying with
the USB 2.0 (Universal Serial Bus Specification Revision 2.0) standards.
4.7.1
Speed Mode and Transfer Type
This LSI’s USB host function supports HS (480 Mbps), FS (12 Mbps) and LS (1.5 Mbps)
speed modes. The speed mode is automatically set by speed negotiations performed on
resetting the bus.
All transfer types stipulated in the USB 2.0 standard are supported, including control
transfers, bulk transfers, interrupt transfers, and isochronous transfers.
4.7.2
Resources
4.7.2.1
Channels
In the LSI USB host functions, sets of register settings for transfers with end
points on a one-to-one basis are called channels. The LSI USB host function
features one dedicated channel for control transfers, one dedicated channel for
bulk transfers, and four general channels that support bulk transfers, interrupt
transfers, and isochronous transfers. The endpoint number, maximum packet
size, and transfer direction (IN/OUT) can be set as desired for all channels.
Transfers are also possible for a number of endpoints exceeding the channel
number using software-based time-multiplexing for the channels.
4.7.2.2
FIFO
Each port on the LSI includes 4.5 kB of FIFO for use with USB data transfers.
This forms the data transfer route with USB. The FIFO capacity for each
channel can be assigned as desired by the software. For example, to improve
performance, assign a FIFO area of adequate size to the endpoints for bulk
transfers.
4.7.3
Data Flow
The channels are assigned to FIFO areas on a one-to-one basis. Transactions are sent
automatically to USB, depending on the FIFO effective free capacity (for IN transfers) or
effective data quantity (for OUT transfers). The software does not need to be directly
involved in individual transactions, allowing USB data transfers to be controlled as data
flow at the FIFO.
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