參數(shù)資料
型號(hào)： S1R72V18B10
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA121
封裝： PLASTIC, FBGA-121
文件頁(yè)數(shù)： 3/37頁(yè)
文件大?。?/td> 365K
代理商： S1R72V18B10
4. Explanation of Functions
6
EPSON
S1R72V18 Data Sheet (Rev. 1.00)
4.4
Power Management
This LSI includes a power management function featuring two power management states for each
port, SLEEP and ACTIVE, together with the CPU_Cut power management state common for the
chip. (See Figure 4-3.)
All function blocks are active in the ACTIVE state, whereas only the bare minimum circuits
necessary for restarting from standby mode are active in SLEEP state. CPU_Cut mode minimizes
power consumption attributable to the CPU-I/F input buffer.
Port 0 ACTIVE
Port 1 ACTIVE
Active
Inactive
CPU
-I/F
FIFO
SIE_0
MTM_0
SIE_1
MTM_1
OSC
PLL60
*
The CPU-I/F is only partially active in SLEEP state.
The asynchronous access register can be accessed.
** CPU-I/F operation is suspended in CPU_Cut to minimize
power consumption attributable to the I/O input buffer.
Port 0 ACTIVE
Port 1 SLEEP
CPU
-I/F
FIFO
SIE_0
MTM_0
SIE_1
MTM_1
OSC
PLL60
Port 0 SLEEP
Port 1 ACTIVE
CPU
-I/F
FIFO
SIE_1
MTM_1
SIE_0
MTM_0
OSC
PLL60
Port 0 SLEEP
Port 1 SLEEP
CPU
-I/F*
FIFO
SIE_1
MTM_1
SIE_0
MTM_0
OSC
PLL60
Port 0 CPU_Cut
Port 1 CPU_Cut
CPU
-I/F**
FIFO
SIE_1
MTM_1
SIE_0
MTM_0
OSC
PLL60
Figure 4-3
Power management states
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