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參數(shù)資料
| 型號： | S1M8657X01-E0T0 |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, LQFP-48 |
| 文件頁數(shù)： | 13/34頁 |
| 文件大小： | 281K |
| 代理商： | S1M8657X01-E0T0 |
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S1M8657
TX IF/BBA WITH AGC
20
[Order of divide ratio calculation]
VCO = 260.76MHz, TCXO = 19.68MHz, Phase detect frequency = 1.23MHz, Prescaler = 16
1) Determine the value of N : N = fVCO/fPD = 260.76MHz/1.23MHz = 212
2) Determine the value of A : A = Int(N/P) = Int(212/16) = 13
When this value is set in the register, the value of A-1(12) must be placed.
Binary value is 000001100.
3) Determine the value of B : B = N - P
× A = 121 - 16 × 13 = 4
4) Determine the value of R : R = fREF/fPD = 19.68MHz/1.23MHz = 16
The R register value is R-1 so 15 must be written. Binary value is 0000001111.
The external PDISET resistance determines the charge pump from PDOUT. This resistance determines the
current flowing between PDISET and GND as follows.
Io = Rset/0.64V
Io is the charge-pump current when the PLL is locked. If the resistance is 39k
, Io becomes 16uA.
The charge-pump current is classified into lock mode current and acquisition mode current to quickly stabilize the
un-locked IC. The charge-pump current of the acquistion mode flows 10 times faster than that of the lock mode,
thus providing faster stability. Although the Lock-Acquisition current can be changed from one to the other, the
SPI PLL_Mode [4:3] register value can be used to permanently set the charge-pump current as either acquisition
mode current or lock mode current. However, the type of current to be set should be carefully decided based on
the amount of surrounding noise flowing into VCO. The charge-pump polarity can be change with PLLR1[4] to
respond to the various conditions of the capacitor, whose value can be changed "+' or "-" for the varactor signal,
according to how the VCO is used. A lock pin has been prepared to indicate that lock has occurred because the
Tx frequency has entered the set band. This pin can be used to select from either the open-drain output or CMOS
output. If the OPEN_DRAIN output is selected, an external 10k
Pull up resistance is required. PLL_MODE[6]
can be set to select the output type. Lock -unlock states can be determined by counting how many times the
phase difference between the signal in the IC and the reference signal matches within the set phase difference
band. Two criteria which can be used to detemine the lock are the phase difference band and the frequency of
phase match during a set period. Here the user can select the frequency of phase match, the purpose of which is
to determine whether or not the lock is a stable lock or a temporary lock condition. Namely, the lock condition
,when there are many phase matches, is a very stable condition, but it requires time. The phase difference here
refers to the phase difference between the N-counter output fv and R-counter output f
R. Whether or not to cancel
the lock condition can be decided by determining how many times 2 phase differences fall within the set range
within a specified duration. PLLR1[7:5] SPI register is used to set the phase match or unmatch frequency limit.
Here , this limit is called the Lock-length, which is determined as follows:
fR is the reference frequency in the phase comparator.
fR = fTCXO/R, fTCXO is the basic TCXO frequency, R is the divide ratio for the basic TCXO frequency(R-Counter)
fv is the VCO dividing frequency which is compared to the reference frequency in the phase comparator.
fv = (fVCO + fERROR)/N, where fVCO is the VCO basic frequency and fERROR is the allowable maximum frequency
range.
Based on the above equation, the number of PD pulses required for the VCO frequency
in a set band is
N
PD = 2 × TTCXO/(1/fR - 1/fV), TTCXO is the period of the TCXO basic frequency.
The number of TCXO pulses for the VCO frequency in a set range is
N
TCXO = R × NPD
where, Lock-length M = log2(N
TCXO) - 13
Lock counter length is 2
(M+13).
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