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參數(shù)資料
| 型號： | S1D13600F00A |
| 元件分類： | 顯示控制器 |
| 英文描述： | CRT OR FLAT PNL GRPH DSPL CTLR, PQFP64 |
| 封裝： | QFP6-64 |
| 文件頁數(shù)： | 23/29頁 |
| 文件大?。?/td> | 190K |
| 代理商： | S1D13600F00A |
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S1D13600 Series
Rev. 2.3
EPSON
1–3
S1D13600
(1) 3.3 V operational low power LCD Controller Chip.
(2) receives Data from CPU.
(3) stores the Display Data into SRAM.
(4) reads the Data written in the SRAM to update LCD Display.
(5) transfers the read Data to LCD Module automatically.
(6) controls entering to Doze Mode and returning to Active Mode automatically.
(7) supports local oscillation or low frequency input to realize the Ultra Low Power LCD Display
Subsystem.
(8) supports Hardware Suspend Mode.
LCD Module
(1) 3.3 V operational low power LCD Module.
(2) consists of Seiko Epson’s RAM integrated Segment Drivers, Common Drivers and an LCD panel.
(3) The LCD Module enters into Power Save Mode automatically, if “XSCLU” is not provided.
SRAM
(1) S1D13600 uses the SRAM to store the Display Data written by CPU in order to arbitrate between
CPU access and LCD Display refresh.
(2) has to be 3.3 V operational.
S1D13600 Internal Block Diagram
The following figure shows an overview of the LCD Controller chip S1D13600.
Address Generator
For CPU Access
Address Generator
For Display Refresh
Address
Selector
Memory Controller
S1D13600
LCD Timing Generator
CPU
Interf
ace
Power Management Unit
External Parts for Local Oscillation
OSC1
TST2
OSC2
OSC3
Test Unit
10
D[0:7]
E
CS
DT/CM
SLEEP
RESET
VD[0:7]
VA[0:14]
VCS[0:1]
VOE
VR/W
YD
LP
XD[0:7]
XSCLU
FR
DOFF
Figure 2. S1D13600 Internal Block Diagram
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