參數(shù)資料
型號(hào)： S1D13600F00A
元件分類： 顯示控制器
英文描述： CRT OR FLAT PNL GRPH DSPL CTLR, PQFP64
封裝： QFP6-64
文件頁(yè)數(shù)： 2/29頁(yè)
文件大?。?/td> 190K
代理商： S1D13600F00A
S1D13600 Series
1–10
EPSON
Rev. 2.3
Oscillation
The oscillation pins are used to generate the low frequency which directly generates the “LP” signal.
Table 5. Oscillation Pin Description
Pin Name
Typ.
Pin No.
Drv
Description
The pin is connected to the one node of the
OSC1
I
61
COSC
capacitance and the one node of the resistance.
If an external oscillator is used as a clock source,
then this pin is the clock input.
This pin is connected to the other node of the
OSC2
O
62
OOSC
capacitance. If an external oscillator is used as a
clock source, then this pin should be left
unconnected.
This pin is connected to the other node of the
OSC3
O
63
OOSC
resistance. If an external oscillator is used as a
clock source, then this pin should be left
unconnected.
Test
The test signals are prepared for testing the chip itself.
Table 6. Test Pin Description
Pin Name
Typ.
Pin No.
Drv
Description
NC
—
12, 17,
—
NC pins are not connected to the chip. These pins
19
should be left unconnected.
TST2
O
16
O1
This pin should be left unconnected.
Power Supply
Pin Name
Typ.
Pin No.
Drv
Description
VDD
P
1, 33
VDD supply for the chip. Normally 3.3 volt.
VSS
P
32, 64
VSS supply for the chip. Normally 0 volt.
Table 7. Power Supply Pin Description
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