參數(shù)資料
型號： S1D13600F00A
元件分類： 顯示控制器
英文描述： CRT OR FLAT PNL GRPH DSPL CTLR, PQFP64
封裝： QFP6-64
文件頁數(shù)： 11/29頁
文件大?。?/td> 190K
代理商： S1D13600F00A
S1D13600 Series
Rev. 2.3
EPSON
1–19
Oscillation Timing
Table 16. LCD Interface Timing
Figure 8. LCD Interface Timing
Parameter
Symbol
Min.
Typ.
Max.
Units
“OSC1” period
tcycOSC
20
41.7
50
s
tOSC = 50 kHz fOSC = 24 kHz fOSC = 20 kHz
“OSC1” LOW width if external
tlOSC
0.5
tcycOSC
s
oscillation is used.
“OSC1” HIGH width if external
thOSC
0.5
tcycOSC
s
oscillation is used.
OSC1
tcycOSC
tlOSC
thOSC
8. OPERATION DESCRIPTION
CPU Write Data Transfer
The following figure gives a basic timing for S1D13600 to receive the CPU Write Data and relationship
between CPU Data and pixels on the LCD panel. It is assumed that both CPU Write Start Address and
Display Refresh Start Address are the same and the 320
× 200 dot LCD is used in the following figure.
(1) The rising edge of “
CS” is used for S1D13600 to latch the CPU data.
(2) The CPU Data Write, after the “Display Data Write” command is executed, will be stored in the
SRAM according to the internal CPU Write Address.
(3) The first 40 Byte data will be stored in SRAM and displayed continuously on the same line.
(4) The data will be displayed at the most left position on the next line on the panel every 40 Byte data.
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